1 /* 2 * Copyright (c) 2018, Impinj, Inc. 3 * 4 * i.MX7 SoC definitions 5 * 6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef FSL_IMX7_H 20 #define FSL_IMX7_H 21 22 #include "hw/arm/boot.h" 23 #include "hw/cpu/a15mpcore.h" 24 #include "hw/intc/imx_gpcv2.h" 25 #include "hw/misc/imx7_ccm.h" 26 #include "hw/misc/imx7_snvs.h" 27 #include "hw/misc/imx7_gpr.h" 28 #include "hw/misc/imx6_src.h" 29 #include "hw/watchdog/wdt_imx2.h" 30 #include "hw/gpio/imx_gpio.h" 31 #include "hw/char/imx_serial.h" 32 #include "hw/timer/imx_gpt.h" 33 #include "hw/timer/imx_epit.h" 34 #include "hw/i2c/imx_i2c.h" 35 #include "hw/sd/sdhci.h" 36 #include "hw/ssi/imx_spi.h" 37 #include "hw/net/imx_fec.h" 38 #include "hw/pci-host/designware.h" 39 #include "hw/usb/chipidea.h" 40 #include "cpu.h" 41 #include "qom/object.h" 42 43 #define TYPE_FSL_IMX7 "fsl-imx7" 44 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7) 45 46 enum FslIMX7Configuration { 47 FSL_IMX7_NUM_CPUS = 2, 48 FSL_IMX7_NUM_UARTS = 7, 49 FSL_IMX7_NUM_ETHS = 2, 50 FSL_IMX7_ETH_NUM_TX_RINGS = 3, 51 FSL_IMX7_NUM_USDHCS = 3, 52 FSL_IMX7_NUM_WDTS = 4, 53 FSL_IMX7_NUM_GPTS = 4, 54 FSL_IMX7_NUM_IOMUXCS = 2, 55 FSL_IMX7_NUM_GPIOS = 7, 56 FSL_IMX7_NUM_I2CS = 4, 57 FSL_IMX7_NUM_ECSPIS = 4, 58 FSL_IMX7_NUM_USBS = 3, 59 FSL_IMX7_NUM_ADCS = 2, 60 }; 61 62 struct FslIMX7State { 63 /*< private >*/ 64 DeviceState parent_obj; 65 66 /*< public >*/ 67 ARMCPU cpu[FSL_IMX7_NUM_CPUS]; 68 A15MPPrivState a7mpcore; 69 IMXGPTState gpt[FSL_IMX7_NUM_GPTS]; 70 IMXGPIOState gpio[FSL_IMX7_NUM_GPIOS]; 71 IMX7CCMState ccm; 72 IMX7AnalogState analog; 73 IMX7SNVSState snvs; 74 IMXGPCv2State gpcv2; 75 IMXSPIState spi[FSL_IMX7_NUM_ECSPIS]; 76 IMXI2CState i2c[FSL_IMX7_NUM_I2CS]; 77 IMXSerialState uart[FSL_IMX7_NUM_UARTS]; 78 IMXFECState eth[FSL_IMX7_NUM_ETHS]; 79 SDHCIState usdhc[FSL_IMX7_NUM_USDHCS]; 80 IMX2WdtState wdt[FSL_IMX7_NUM_WDTS]; 81 IMX7GPRState gpr; 82 ChipideaState usb[FSL_IMX7_NUM_USBS]; 83 DesignwarePCIEHost pcie; 84 uint32_t phy_num[FSL_IMX7_NUM_ETHS]; 85 }; 86 87 enum FslIMX7MemoryMap { 88 FSL_IMX7_MMDC_ADDR = 0x80000000, 89 FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL, 90 91 FSL_IMX7_GPIO1_ADDR = 0x30200000, 92 FSL_IMX7_GPIO2_ADDR = 0x30210000, 93 FSL_IMX7_GPIO3_ADDR = 0x30220000, 94 FSL_IMX7_GPIO4_ADDR = 0x30230000, 95 FSL_IMX7_GPIO5_ADDR = 0x30240000, 96 FSL_IMX7_GPIO6_ADDR = 0x30250000, 97 FSL_IMX7_GPIO7_ADDR = 0x30260000, 98 99 FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, 100 101 FSL_IMX7_WDOG1_ADDR = 0x30280000, 102 FSL_IMX7_WDOG2_ADDR = 0x30290000, 103 FSL_IMX7_WDOG3_ADDR = 0x302A0000, 104 FSL_IMX7_WDOG4_ADDR = 0x302B0000, 105 106 FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, 107 108 FSL_IMX7_GPT1_ADDR = 0x302D0000, 109 FSL_IMX7_GPT2_ADDR = 0x302E0000, 110 FSL_IMX7_GPT3_ADDR = 0x302F0000, 111 FSL_IMX7_GPT4_ADDR = 0x30300000, 112 113 FSL_IMX7_IOMUXC_ADDR = 0x30330000, 114 FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, 115 FSL_IMX7_IOMUXCn_SIZE = 0x1000, 116 117 FSL_IMX7_OCOTP_ADDR = 0x30350000, 118 FSL_IMX7_OCOTP_SIZE = 0x10000, 119 120 FSL_IMX7_ANALOG_ADDR = 0x30360000, 121 FSL_IMX7_SNVS_ADDR = 0x30370000, 122 FSL_IMX7_CCM_ADDR = 0x30380000, 123 124 FSL_IMX7_SRC_ADDR = 0x30390000, 125 FSL_IMX7_SRC_SIZE = 0x1000, 126 127 FSL_IMX7_ADC1_ADDR = 0x30610000, 128 FSL_IMX7_ADC2_ADDR = 0x30620000, 129 FSL_IMX7_ADCn_SIZE = 0x1000, 130 131 FSL_IMX7_PWM1_ADDR = 0x30660000, 132 FSL_IMX7_PWM2_ADDR = 0x30670000, 133 FSL_IMX7_PWM3_ADDR = 0x30680000, 134 FSL_IMX7_PWM4_ADDR = 0x30690000, 135 FSL_IMX7_PWMn_SIZE = 0x10000, 136 137 FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, 138 FSL_IMX7_PCIE_PHY_SIZE = 0x10000, 139 140 FSL_IMX7_GPC_ADDR = 0x303A0000, 141 142 FSL_IMX7_CAAM_ADDR = 0x30900000, 143 FSL_IMX7_CAAM_SIZE = 0x40000, 144 145 FSL_IMX7_CAN1_ADDR = 0x30A00000, 146 FSL_IMX7_CAN2_ADDR = 0x30A10000, 147 FSL_IMX7_CANn_SIZE = 0x10000, 148 149 FSL_IMX7_I2C1_ADDR = 0x30A20000, 150 FSL_IMX7_I2C2_ADDR = 0x30A30000, 151 FSL_IMX7_I2C3_ADDR = 0x30A40000, 152 FSL_IMX7_I2C4_ADDR = 0x30A50000, 153 154 FSL_IMX7_ECSPI1_ADDR = 0x30820000, 155 FSL_IMX7_ECSPI2_ADDR = 0x30830000, 156 FSL_IMX7_ECSPI3_ADDR = 0x30840000, 157 FSL_IMX7_ECSPI4_ADDR = 0x30630000, 158 159 FSL_IMX7_LCDIF_ADDR = 0x30730000, 160 FSL_IMX7_LCDIF_SIZE = 0x1000, 161 162 FSL_IMX7_UART1_ADDR = 0x30860000, 163 /* 164 * Some versions of the reference manual claim that UART2 is @ 165 * 0x30870000, but experiments with HW + DT files in upstream 166 * Linux kernel show that not to be true and that block is 167 * acutally located @ 0x30890000 168 */ 169 FSL_IMX7_UART2_ADDR = 0x30890000, 170 FSL_IMX7_UART3_ADDR = 0x30880000, 171 FSL_IMX7_UART4_ADDR = 0x30A60000, 172 FSL_IMX7_UART5_ADDR = 0x30A70000, 173 FSL_IMX7_UART6_ADDR = 0x30A80000, 174 FSL_IMX7_UART7_ADDR = 0x30A90000, 175 176 FSL_IMX7_SAI1_ADDR = 0x308A0000, 177 FSL_IMX7_SAI2_ADDR = 0x308B0000, 178 FSL_IMX7_SAI3_ADDR = 0x308C0000, 179 FSL_IMX7_SAIn_SIZE = 0x10000, 180 181 FSL_IMX7_ENET1_ADDR = 0x30BE0000, 182 FSL_IMX7_ENET2_ADDR = 0x30BF0000, 183 184 FSL_IMX7_USB1_ADDR = 0x30B10000, 185 FSL_IMX7_USBMISC1_ADDR = 0x30B10200, 186 FSL_IMX7_USB2_ADDR = 0x30B20000, 187 FSL_IMX7_USBMISC2_ADDR = 0x30B20200, 188 FSL_IMX7_USB3_ADDR = 0x30B30000, 189 FSL_IMX7_USBMISC3_ADDR = 0x30B30200, 190 FSL_IMX7_USBMISCn_SIZE = 0x200, 191 192 FSL_IMX7_USDHC1_ADDR = 0x30B40000, 193 FSL_IMX7_USDHC2_ADDR = 0x30B50000, 194 FSL_IMX7_USDHC3_ADDR = 0x30B60000, 195 196 FSL_IMX7_SDMA_ADDR = 0x30BD0000, 197 FSL_IMX7_SDMA_SIZE = 0x1000, 198 199 FSL_IMX7_A7MPCORE_ADDR = 0x31000000, 200 FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000, 201 202 FSL_IMX7_PCIE_REG_ADDR = 0x33800000, 203 FSL_IMX7_PCIE_REG_SIZE = 16 * 1024, 204 205 FSL_IMX7_GPR_ADDR = 0x30340000, 206 207 FSL_IMX7_DMA_APBH_ADDR = 0x33000000, 208 FSL_IMX7_DMA_APBH_SIZE = 0x2000, 209 }; 210 211 enum FslIMX7IRQs { 212 FSL_IMX7_USDHC1_IRQ = 22, 213 FSL_IMX7_USDHC2_IRQ = 23, 214 FSL_IMX7_USDHC3_IRQ = 24, 215 216 FSL_IMX7_UART1_IRQ = 26, 217 FSL_IMX7_UART2_IRQ = 27, 218 FSL_IMX7_UART3_IRQ = 28, 219 FSL_IMX7_UART4_IRQ = 29, 220 FSL_IMX7_UART5_IRQ = 30, 221 FSL_IMX7_UART6_IRQ = 16, 222 223 FSL_IMX7_ECSPI1_IRQ = 31, 224 FSL_IMX7_ECSPI2_IRQ = 32, 225 FSL_IMX7_ECSPI3_IRQ = 33, 226 FSL_IMX7_ECSPI4_IRQ = 34, 227 228 FSL_IMX7_I2C1_IRQ = 35, 229 FSL_IMX7_I2C2_IRQ = 36, 230 FSL_IMX7_I2C3_IRQ = 37, 231 FSL_IMX7_I2C4_IRQ = 38, 232 233 FSL_IMX7_USB1_IRQ = 43, 234 FSL_IMX7_USB2_IRQ = 42, 235 FSL_IMX7_USB3_IRQ = 40, 236 237 FSL_IMX7_GPT1_IRQ = 55, 238 FSL_IMX7_GPT2_IRQ = 54, 239 FSL_IMX7_GPT3_IRQ = 53, 240 FSL_IMX7_GPT4_IRQ = 52, 241 242 FSL_IMX7_GPIO1_LOW_IRQ = 64, 243 FSL_IMX7_GPIO1_HIGH_IRQ = 65, 244 FSL_IMX7_GPIO2_LOW_IRQ = 66, 245 FSL_IMX7_GPIO2_HIGH_IRQ = 67, 246 FSL_IMX7_GPIO3_LOW_IRQ = 68, 247 FSL_IMX7_GPIO3_HIGH_IRQ = 69, 248 FSL_IMX7_GPIO4_LOW_IRQ = 70, 249 FSL_IMX7_GPIO4_HIGH_IRQ = 71, 250 FSL_IMX7_GPIO5_LOW_IRQ = 72, 251 FSL_IMX7_GPIO5_HIGH_IRQ = 73, 252 FSL_IMX7_GPIO6_LOW_IRQ = 74, 253 FSL_IMX7_GPIO6_HIGH_IRQ = 75, 254 FSL_IMX7_GPIO7_LOW_IRQ = 76, 255 FSL_IMX7_GPIO7_HIGH_IRQ = 77, 256 257 FSL_IMX7_WDOG1_IRQ = 78, 258 FSL_IMX7_WDOG2_IRQ = 79, 259 FSL_IMX7_WDOG3_IRQ = 10, 260 FSL_IMX7_WDOG4_IRQ = 109, 261 262 FSL_IMX7_PCI_INTA_IRQ = 125, 263 FSL_IMX7_PCI_INTB_IRQ = 124, 264 FSL_IMX7_PCI_INTC_IRQ = 123, 265 FSL_IMX7_PCI_INTD_IRQ = 122, 266 267 FSL_IMX7_UART7_IRQ = 126, 268 269 #define FSL_IMX7_ENET_IRQ(i, n) ((n) + ((i) ? 100 : 118)) 270 271 FSL_IMX7_MAX_IRQ = 128, 272 }; 273 274 #endif /* FSL_IMX7_H */ 275