1 /* 2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6ul SoC definitions 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #ifndef FSL_IMX6UL_H 18 #define FSL_IMX6UL_H 19 20 #include "hw/arm/boot.h" 21 #include "hw/cpu/a15mpcore.h" 22 #include "hw/misc/imx6ul_ccm.h" 23 #include "hw/misc/imx6_src.h" 24 #include "hw/misc/imx7_snvs.h" 25 #include "hw/misc/imx7_gpr.h" 26 #include "hw/intc/imx_gpcv2.h" 27 #include "hw/watchdog/wdt_imx2.h" 28 #include "hw/gpio/imx_gpio.h" 29 #include "hw/char/imx_serial.h" 30 #include "hw/timer/imx_gpt.h" 31 #include "hw/timer/imx_epit.h" 32 #include "hw/i2c/imx_i2c.h" 33 #include "hw/gpio/imx_gpio.h" 34 #include "hw/sd/sdhci.h" 35 #include "hw/ssi/imx_spi.h" 36 #include "hw/net/imx_fec.h" 37 #include "hw/usb/chipidea.h" 38 #include "hw/usb/imx-usb-phy.h" 39 #include "exec/memory.h" 40 #include "cpu.h" 41 42 #define TYPE_FSL_IMX6UL "fsl,imx6ul" 43 #define FSL_IMX6UL(obj) OBJECT_CHECK(FslIMX6ULState, (obj), TYPE_FSL_IMX6UL) 44 45 enum FslIMX6ULConfiguration { 46 FSL_IMX6UL_NUM_CPUS = 1, 47 FSL_IMX6UL_NUM_UARTS = 8, 48 FSL_IMX6UL_NUM_ETHS = 2, 49 FSL_IMX6UL_ETH_NUM_TX_RINGS = 2, 50 FSL_IMX6UL_NUM_USDHCS = 2, 51 FSL_IMX6UL_NUM_WDTS = 3, 52 FSL_IMX6UL_NUM_GPTS = 2, 53 FSL_IMX6UL_NUM_EPITS = 2, 54 FSL_IMX6UL_NUM_IOMUXCS = 2, 55 FSL_IMX6UL_NUM_GPIOS = 5, 56 FSL_IMX6UL_NUM_I2CS = 4, 57 FSL_IMX6UL_NUM_ECSPIS = 4, 58 FSL_IMX6UL_NUM_ADCS = 2, 59 FSL_IMX6UL_NUM_USB_PHYS = 2, 60 FSL_IMX6UL_NUM_USBS = 2, 61 }; 62 63 typedef struct FslIMX6ULState { 64 /*< private >*/ 65 DeviceState parent_obj; 66 67 /*< public >*/ 68 ARMCPU cpu; 69 A15MPPrivState a7mpcore; 70 IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS]; 71 IMXEPITState epit[FSL_IMX6UL_NUM_EPITS]; 72 IMXGPIOState gpio[FSL_IMX6UL_NUM_GPIOS]; 73 IMX6ULCCMState ccm; 74 IMX6SRCState src; 75 IMX7SNVSState snvs; 76 IMXGPCv2State gpcv2; 77 IMX7GPRState gpr; 78 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS]; 79 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS]; 80 IMXSerialState uart[FSL_IMX6UL_NUM_UARTS]; 81 IMXFECState eth[FSL_IMX6UL_NUM_ETHS]; 82 SDHCIState usdhc[FSL_IMX6UL_NUM_USDHCS]; 83 IMX2WdtState wdt[FSL_IMX6UL_NUM_WDTS]; 84 IMXUSBPHYState usbphy[FSL_IMX6UL_NUM_USB_PHYS]; 85 ChipideaState usb[FSL_IMX6UL_NUM_USBS]; 86 MemoryRegion rom; 87 MemoryRegion caam; 88 MemoryRegion ocram; 89 MemoryRegion ocram_alias; 90 } FslIMX6ULState; 91 92 enum FslIMX6ULMemoryMap { 93 FSL_IMX6UL_MMDC_ADDR = 0x80000000, 94 FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL, 95 96 FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000, 97 FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000, 98 FSL_IMX6UL_EIM_CS_ADDR = 0x50000000, 99 FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000, 100 FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000, 101 102 /* AIPS-2 */ 103 FSL_IMX6UL_UART6_ADDR = 0x021FC000, 104 FSL_IMX6UL_I2C4_ADDR = 0x021F8000, 105 FSL_IMX6UL_UART5_ADDR = 0x021F4000, 106 FSL_IMX6UL_UART4_ADDR = 0x021F0000, 107 FSL_IMX6UL_UART3_ADDR = 0x021EC000, 108 FSL_IMX6UL_UART2_ADDR = 0x021E8000, 109 FSL_IMX6UL_WDOG3_ADDR = 0x021E4000, 110 FSL_IMX6UL_QSPI_ADDR = 0x021E0000, 111 FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000, 112 FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000, 113 FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000, 114 FSL_IMX6UL_TZASC_ADDR = 0x021D0000, 115 FSL_IMX6UL_PXP_ADDR = 0x021CC000, 116 FSL_IMX6UL_LCDIF_ADDR = 0x021C8000, 117 FSL_IMX6UL_CSI_ADDR = 0x021C4000, 118 FSL_IMX6UL_CSU_ADDR = 0x021C0000, 119 FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000, 120 FSL_IMX6UL_EIM_ADDR = 0x021B8000, 121 FSL_IMX6UL_SIM2_ADDR = 0x021B4000, 122 FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000, 123 FSL_IMX6UL_ROMCP_ADDR = 0x021AC000, 124 FSL_IMX6UL_I2C3_ADDR = 0x021A8000, 125 FSL_IMX6UL_I2C2_ADDR = 0x021A4000, 126 FSL_IMX6UL_I2C1_ADDR = 0x021A0000, 127 FSL_IMX6UL_ADC2_ADDR = 0x0219C000, 128 FSL_IMX6UL_ADC1_ADDR = 0x02198000, 129 FSL_IMX6UL_USDHC2_ADDR = 0x02194000, 130 FSL_IMX6UL_USDHC1_ADDR = 0x02190000, 131 FSL_IMX6UL_SIM1_ADDR = 0x0218C000, 132 FSL_IMX6UL_ENET1_ADDR = 0x02188000, 133 FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800, 134 FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000, 135 FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000, 136 FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000, 137 FSL_IMX6UL_CAAM_ADDR = 0x02140000, 138 FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000, 139 140 /* AIPS-1 */ 141 FSL_IMX6UL_PWM8_ADDR = 0x020FC000, 142 FSL_IMX6UL_PWM7_ADDR = 0x020F8000, 143 FSL_IMX6UL_PWM6_ADDR = 0x020F4000, 144 FSL_IMX6UL_PWM5_ADDR = 0x020F0000, 145 FSL_IMX6UL_SDMA_ADDR = 0x020EC000, 146 FSL_IMX6UL_GPT2_ADDR = 0x020E8000, 147 FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000, 148 FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000, 149 FSL_IMX6UL_GPC_ADDR = 0x020DC000, 150 FSL_IMX6UL_SRC_ADDR = 0x020D8000, 151 FSL_IMX6UL_EPIT2_ADDR = 0x020D4000, 152 FSL_IMX6UL_EPIT1_ADDR = 0x020D0000, 153 FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000, 154 FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000, 155 FSL_IMX6UL_USBPHY2_SIZE = (4 * 1024), 156 FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000, 157 FSL_IMX6UL_USBPHY1_SIZE = (4 * 1024), 158 FSL_IMX6UL_ANALOG_ADDR = 0x020C8000, 159 FSL_IMX6UL_CCM_ADDR = 0x020C4000, 160 FSL_IMX6UL_WDOG2_ADDR = 0x020C0000, 161 FSL_IMX6UL_WDOG1_ADDR = 0x020BC000, 162 FSL_IMX6UL_KPP_ADDR = 0x020B8000, 163 FSL_IMX6UL_ENET2_ADDR = 0x020B4000, 164 FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000, 165 FSL_IMX6UL_GPIO5_ADDR = 0x020AC000, 166 FSL_IMX6UL_GPIO4_ADDR = 0x020A8000, 167 FSL_IMX6UL_GPIO3_ADDR = 0x020A4000, 168 FSL_IMX6UL_GPIO2_ADDR = 0x020A0000, 169 FSL_IMX6UL_GPIO1_ADDR = 0x0209C000, 170 FSL_IMX6UL_GPT1_ADDR = 0x02098000, 171 FSL_IMX6UL_CAN2_ADDR = 0x02094000, 172 FSL_IMX6UL_CAN1_ADDR = 0x02090000, 173 FSL_IMX6UL_PWM4_ADDR = 0x0208C000, 174 FSL_IMX6UL_PWM3_ADDR = 0x02088000, 175 FSL_IMX6UL_PWM2_ADDR = 0x02084000, 176 FSL_IMX6UL_PWM1_ADDR = 0x02080000, 177 FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000, 178 FSL_IMX6UL_BEE_ADDR = 0x02044000, 179 FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000, 180 FSL_IMX6UL_SPBA_ADDR = 0x0203C000, 181 FSL_IMX6UL_ASRC_ADDR = 0x02034000, 182 FSL_IMX6UL_SAI3_ADDR = 0x02030000, 183 FSL_IMX6UL_SAI2_ADDR = 0x0202C000, 184 FSL_IMX6UL_SAI1_ADDR = 0x02028000, 185 FSL_IMX6UL_UART8_ADDR = 0x02024000, 186 FSL_IMX6UL_UART1_ADDR = 0x02020000, 187 FSL_IMX6UL_UART7_ADDR = 0x02018000, 188 FSL_IMX6UL_ECSPI4_ADDR = 0x02014000, 189 FSL_IMX6UL_ECSPI3_ADDR = 0x02010000, 190 FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000, 191 FSL_IMX6UL_ECSPI1_ADDR = 0x02008000, 192 FSL_IMX6UL_SPDIF_ADDR = 0x02004000, 193 194 FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000, 195 FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024), 196 197 FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000, 198 199 FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000, 200 FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000, 201 FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000, 202 FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000, 203 FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000, 204 FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000, 205 FSL_IMX6UL_ROM_ADDR = 0x00000000, 206 FSL_IMX6UL_ROM_SIZE = 0x00018000, 207 }; 208 209 enum FslIMX6ULIRQs { 210 FSL_IMX6UL_IOMUXC_IRQ = 0, 211 FSL_IMX6UL_DAP_IRQ = 1, 212 FSL_IMX6UL_SDMA_IRQ = 2, 213 FSL_IMX6UL_TSC_IRQ = 3, 214 FSL_IMX6UL_SNVS_IRQ = 4, 215 FSL_IMX6UL_LCDIF_IRQ = 5, 216 FSL_IMX6UL_BEE_IRQ = 6, 217 FSL_IMX6UL_CSI_IRQ = 7, 218 FSL_IMX6UL_PXP_IRQ = 8, 219 FSL_IMX6UL_SCTR1_IRQ = 9, 220 FSL_IMX6UL_SCTR2_IRQ = 10, 221 FSL_IMX6UL_WDOG3_IRQ = 11, 222 FSL_IMX6UL_APBH_DMA_IRQ = 13, 223 FSL_IMX6UL_WEIM_IRQ = 14, 224 FSL_IMX6UL_RAWNAND1_IRQ = 15, 225 FSL_IMX6UL_RAWNAND2_IRQ = 16, 226 FSL_IMX6UL_UART6_IRQ = 17, 227 FSL_IMX6UL_SRTC_IRQ = 19, 228 FSL_IMX6UL_SRTC_SEC_IRQ = 20, 229 FSL_IMX6UL_CSU_IRQ = 21, 230 FSL_IMX6UL_USDHC1_IRQ = 22, 231 FSL_IMX6UL_USDHC2_IRQ = 23, 232 FSL_IMX6UL_SAI3_IRQ = 24, 233 FSL_IMX6UL_SAI32_IRQ = 25, 234 235 FSL_IMX6UL_UART1_IRQ = 26, 236 FSL_IMX6UL_UART2_IRQ = 27, 237 FSL_IMX6UL_UART3_IRQ = 28, 238 FSL_IMX6UL_UART4_IRQ = 29, 239 FSL_IMX6UL_UART5_IRQ = 30, 240 241 FSL_IMX6UL_ECSPI1_IRQ = 31, 242 FSL_IMX6UL_ECSPI2_IRQ = 32, 243 FSL_IMX6UL_ECSPI3_IRQ = 33, 244 FSL_IMX6UL_ECSPI4_IRQ = 34, 245 246 FSL_IMX6UL_I2C4_IRQ = 35, 247 FSL_IMX6UL_I2C1_IRQ = 36, 248 FSL_IMX6UL_I2C2_IRQ = 37, 249 FSL_IMX6UL_I2C3_IRQ = 38, 250 251 FSL_IMX6UL_UART7_IRQ = 39, 252 FSL_IMX6UL_UART8_IRQ = 40, 253 254 FSL_IMX6UL_USB1_IRQ = 43, 255 FSL_IMX6UL_USB2_IRQ = 42, 256 FSL_IMX6UL_USB_PHY1_IRQ = 44, 257 FSL_IMX6UL_USB_PHY2_IRQ = 45, 258 259 FSL_IMX6UL_CAAM_JQ2_IRQ = 46, 260 FSL_IMX6UL_CAAM_ERR_IRQ = 47, 261 FSL_IMX6UL_CAAM_RTIC_IRQ = 48, 262 FSL_IMX6UL_TEMP_IRQ = 49, 263 FSL_IMX6UL_ASRC_IRQ = 50, 264 FSL_IMX6UL_SPDIF_IRQ = 52, 265 FSL_IMX6UL_PMU_REG_IRQ = 54, 266 FSL_IMX6UL_GPT1_IRQ = 55, 267 268 FSL_IMX6UL_EPIT1_IRQ = 56, 269 FSL_IMX6UL_EPIT2_IRQ = 57, 270 271 FSL_IMX6UL_GPIO1_INT7_IRQ = 58, 272 FSL_IMX6UL_GPIO1_INT6_IRQ = 59, 273 FSL_IMX6UL_GPIO1_INT5_IRQ = 60, 274 FSL_IMX6UL_GPIO1_INT4_IRQ = 61, 275 FSL_IMX6UL_GPIO1_INT3_IRQ = 62, 276 FSL_IMX6UL_GPIO1_INT2_IRQ = 63, 277 FSL_IMX6UL_GPIO1_INT1_IRQ = 64, 278 FSL_IMX6UL_GPIO1_INT0_IRQ = 65, 279 FSL_IMX6UL_GPIO1_LOW_IRQ = 66, 280 FSL_IMX6UL_GPIO1_HIGH_IRQ = 67, 281 FSL_IMX6UL_GPIO2_LOW_IRQ = 68, 282 FSL_IMX6UL_GPIO2_HIGH_IRQ = 69, 283 FSL_IMX6UL_GPIO3_LOW_IRQ = 70, 284 FSL_IMX6UL_GPIO3_HIGH_IRQ = 71, 285 FSL_IMX6UL_GPIO4_LOW_IRQ = 72, 286 FSL_IMX6UL_GPIO4_HIGH_IRQ = 73, 287 FSL_IMX6UL_GPIO5_LOW_IRQ = 74, 288 FSL_IMX6UL_GPIO5_HIGH_IRQ = 75, 289 290 FSL_IMX6UL_WDOG1_IRQ = 80, 291 FSL_IMX6UL_WDOG2_IRQ = 81, 292 293 FSL_IMX6UL_KPP_IRQ = 82, 294 295 FSL_IMX6UL_PWM1_IRQ = 83, 296 FSL_IMX6UL_PWM2_IRQ = 84, 297 FSL_IMX6UL_PWM3_IRQ = 85, 298 FSL_IMX6UL_PWM4_IRQ = 86, 299 300 FSL_IMX6UL_CCM1_IRQ = 87, 301 FSL_IMX6UL_CCM2_IRQ = 88, 302 303 FSL_IMX6UL_GPC_IRQ = 89, 304 305 FSL_IMX6UL_SRC_IRQ = 91, 306 307 FSL_IMX6UL_CPU_PERF_IRQ = 94, 308 FSL_IMX6UL_CPU_CTI_IRQ = 95, 309 310 FSL_IMX6UL_SRC_WDOG_IRQ = 96, 311 312 FSL_IMX6UL_SAI1_IRQ = 97, 313 FSL_IMX6UL_SAI2_IRQ = 98, 314 315 FSL_IMX6UL_ADC1_IRQ = 100, 316 FSL_IMX6UL_ADC2_IRQ = 101, 317 318 FSL_IMX6UL_SJC_IRQ = 104, 319 320 FSL_IMX6UL_CAAM_RING0_IRQ = 105, 321 FSL_IMX6UL_CAAM_RING1_IRQ = 106, 322 323 FSL_IMX6UL_QSPI_IRQ = 107, 324 325 FSL_IMX6UL_TZASC_IRQ = 108, 326 327 FSL_IMX6UL_GPT2_IRQ = 109, 328 329 FSL_IMX6UL_CAN1_IRQ = 110, 330 FSL_IMX6UL_CAN2_IRQ = 111, 331 332 FSL_IMX6UL_SIM1_IRQ = 112, 333 FSL_IMX6UL_SIM2_IRQ = 113, 334 335 FSL_IMX6UL_PWM5_IRQ = 114, 336 FSL_IMX6UL_PWM6_IRQ = 115, 337 FSL_IMX6UL_PWM7_IRQ = 116, 338 FSL_IMX6UL_PWM8_IRQ = 117, 339 340 FSL_IMX6UL_ENET1_IRQ = 118, 341 FSL_IMX6UL_ENET1_TIMER_IRQ = 119, 342 FSL_IMX6UL_ENET2_IRQ = 120, 343 FSL_IMX6UL_ENET2_TIMER_IRQ = 121, 344 345 FSL_IMX6UL_PMU_CORE_IRQ = 127, 346 FSL_IMX6UL_MAX_IRQ = 128, 347 }; 348 349 #endif /* FSL_IMX6UL_H */ 350