xref: /openbmc/qemu/include/hw/arm/fsl-imx6.h (revision 7a1dc45af581d2b643cdbf33c01fd96271616fbd)
1  /*
2   * Freescale i.MX31 SoC emulation
3   *
4   * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
5   *
6   * This program is free software; you can redistribute it and/or modify it
7   * under the terms of the GNU General Public License as published by the
8   * Free Software Foundation; either version 2 of the License, or
9   * (at your option) any later version.
10   *
11   * This program is distributed in the hope that it will be useful, but WITHOUT
12   * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13   * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14   * for more details.
15   */
16  
17  #ifndef FSL_IMX6_H
18  #define FSL_IMX6_H
19  
20  #include "hw/cpu/a9mpcore.h"
21  #include "hw/misc/imx6_ccm.h"
22  #include "hw/misc/imx6_src.h"
23  #include "hw/misc/imx7_snvs.h"
24  #include "hw/watchdog/wdt_imx2.h"
25  #include "hw/char/imx_serial.h"
26  #include "hw/timer/imx_gpt.h"
27  #include "hw/timer/imx_epit.h"
28  #include "hw/i2c/imx_i2c.h"
29  #include "hw/gpio/imx_gpio.h"
30  #include "hw/sd/sdhci.h"
31  #include "hw/ssi/imx_spi.h"
32  #include "hw/net/imx_fec.h"
33  #include "hw/usb/chipidea.h"
34  #include "hw/usb/imx-usb-phy.h"
35  #include "hw/pci-host/designware.h"
36  #include "exec/memory.h"
37  #include "cpu.h"
38  #include "qom/object.h"
39  
40  #define TYPE_FSL_IMX6 "fsl-imx6"
41  OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6State, FSL_IMX6)
42  
43  #define FSL_IMX6_NUM_CPUS 4
44  #define FSL_IMX6_NUM_UARTS 5
45  #define FSL_IMX6_NUM_EPITS 2
46  #define FSL_IMX6_NUM_I2CS 3
47  #define FSL_IMX6_NUM_GPIOS 7
48  #define FSL_IMX6_NUM_ESDHCS 4
49  #define FSL_IMX6_NUM_ECSPIS 5
50  #define FSL_IMX6_NUM_WDTS 2
51  #define FSL_IMX6_NUM_USB_PHYS 2
52  #define FSL_IMX6_NUM_USBS 4
53  
54  struct FslIMX6State {
55      /*< private >*/
56      DeviceState parent_obj;
57  
58      /*< public >*/
59      ARMCPU             cpu[FSL_IMX6_NUM_CPUS];
60      A9MPPrivState      a9mpcore;
61      IMX6CCMState       ccm;
62      IMX6SRCState       src;
63      IMX7SNVSState      snvs;
64      IMXSerialState     uart[FSL_IMX6_NUM_UARTS];
65      IMXGPTState        gpt;
66      IMXEPITState       epit[FSL_IMX6_NUM_EPITS];
67      IMXI2CState        i2c[FSL_IMX6_NUM_I2CS];
68      IMXGPIOState       gpio[FSL_IMX6_NUM_GPIOS];
69      SDHCIState         esdhc[FSL_IMX6_NUM_ESDHCS];
70      IMXSPIState        spi[FSL_IMX6_NUM_ECSPIS];
71      IMX2WdtState       wdt[FSL_IMX6_NUM_WDTS];
72      IMXUSBPHYState     usbphy[FSL_IMX6_NUM_USB_PHYS];
73      ChipideaState      usb[FSL_IMX6_NUM_USBS];
74      IMXFECState        eth;
75      DesignwarePCIEHost pcie;
76      MemoryRegion       rom;
77      MemoryRegion       caam;
78      MemoryRegion       ocram;
79      MemoryRegion       ocram_alias;
80      uint32_t           phy_num;
81  };
82  
83  
84  #define FSL_IMX6_MMDC_ADDR 0x10000000
85  #define FSL_IMX6_MMDC_SIZE 0xF0000000
86  #define FSL_IMX6_EIM_MEM_ADDR 0x08000000
87  #define FSL_IMX6_EIM_MEM_SIZE 0x8000000
88  #define FSL_IMX6_IPU_2_ADDR 0x02800000
89  #define FSL_IMX6_IPU_2_SIZE 0x400000
90  #define FSL_IMX6_IPU_1_ADDR 0x02400000
91  #define FSL_IMX6_IPU_1_SIZE 0x400000
92  #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
93  #define FSL_IMX6_MIPI_HSI_SIZE 0x4000
94  #define FSL_IMX6_OPENVG_ADDR 0x02204000
95  #define FSL_IMX6_OPENVG_SIZE 0x4000
96  #define FSL_IMX6_SATA_ADDR 0x02200000
97  #define FSL_IMX6_SATA_SIZE 0x4000
98  #define FSL_IMX6_AIPS_2_ADDR 0x02100000
99  #define FSL_IMX6_AIPS_2_SIZE 0x100000
100  /* AIPS2 */
101  #define FSL_IMX6_UART5_ADDR 0x021F4000
102  #define FSL_IMX6_UART5_SIZE 0x4000
103  #define FSL_IMX6_UART4_ADDR 0x021F0000
104  #define FSL_IMX6_UART4_SIZE 0x4000
105  #define FSL_IMX6_UART3_ADDR 0x021EC000
106  #define FSL_IMX6_UART3_SIZE 0x4000
107  #define FSL_IMX6_UART2_ADDR 0x021E8000
108  #define FSL_IMX6_UART2_SIZE 0x4000
109  #define FSL_IMX6_VDOA_ADDR 0x021E4000
110  #define FSL_IMX6_VDOA_SIZE 0x4000
111  #define FSL_IMX6_MIPI_DSI_ADDR 0x021E0000
112  #define FSL_IMX6_MIPI_DSI_SIZE 0x4000
113  #define FSL_IMX6_MIPI_CSI_ADDR 0x021DC000
114  #define FSL_IMX6_MIPI_CSI_SIZE 0x4000
115  #define FSL_IMX6_AUDMUX_ADDR 0x021D8000
116  #define FSL_IMX6_AUDMUX_SIZE 0x4000
117  #define FSL_IMX6_TZASC2_ADDR 0x021D4000
118  #define FSL_IMX6_TZASC2_SIZE 0x4000
119  #define FSL_IMX6_TZASC1_ADDR 0x021D0000
120  #define FSL_IMX6_TZASC1_SIZE 0x4000
121  #define FSL_IMX6_CSU_ADDR 0x021C0000
122  #define FSL_IMX6_CSU_SIZE 0x4000
123  #define FSL_IMX6_OCOTPCTRL_ADDR 0x021BC000
124  #define FSL_IMX6_OCOTPCTRL_SIZE 0x4000
125  #define FSL_IMX6_EIM_ADDR 0x021B8000
126  #define FSL_IMX6_EIM_SIZE 0x4000
127  #define FSL_IMX6_MMDC1_ADDR 0x021B4000
128  #define FSL_IMX6_MMDC1_SIZE 0x4000
129  #define FSL_IMX6_MMDC0_ADDR 0x021B0000
130  #define FSL_IMX6_MMDC0_SIZE 0x4000
131  #define FSL_IMX6_ROMCP_ADDR 0x021AC000
132  #define FSL_IMX6_ROMCP_SIZE 0x4000
133  #define FSL_IMX6_I2C3_ADDR 0x021A8000
134  #define FSL_IMX6_I2C3_SIZE 0x4000
135  #define FSL_IMX6_I2C2_ADDR 0x021A4000
136  #define FSL_IMX6_I2C2_SIZE 0x4000
137  #define FSL_IMX6_I2C1_ADDR 0x021A0000
138  #define FSL_IMX6_I2C1_SIZE 0x4000
139  #define FSL_IMX6_uSDHC4_ADDR 0x0219C000
140  #define FSL_IMX6_uSDHC4_SIZE 0x4000
141  #define FSL_IMX6_uSDHC3_ADDR 0x02198000
142  #define FSL_IMX6_uSDHC3_SIZE 0x4000
143  #define FSL_IMX6_uSDHC2_ADDR 0x02194000
144  #define FSL_IMX6_uSDHC2_SIZE 0x4000
145  #define FSL_IMX6_uSDHC1_ADDR 0x02190000
146  #define FSL_IMX6_uSDHC1_SIZE 0x4000
147  #define FSL_IMX6_MLB150_ADDR 0x0218C000
148  #define FSL_IMX6_MLB150_SIZE 0x4000
149  #define FSL_IMX6_ENET_ADDR 0x02188000
150  #define FSL_IMX6_ENET_SIZE 0x4000
151  #define FSL_IMX6_USBOH3_USB_ADDR 0x02184000
152  #define FSL_IMX6_USBOH3_USB_SIZE 0x4000
153  #define FSL_IMX6_AIPS2_CFG_ADDR 0x0217C000
154  #define FSL_IMX6_AIPS2_CFG_SIZE 0x4000
155  /* DAP */
156  #define FSL_IMX6_PTF_CTRL_ADDR 0x02160000
157  #define FSL_IMX6_PTF_CTRL_SIZE 0x1000
158  #define FSL_IMX6_PTM3_ADDR 0x0215F000
159  #define FSL_IMX6_PTM3_SIZE 0x1000
160  #define FSL_IMX6_PTM2_ADDR 0x0215E000
161  #define FSL_IMX6_PTM2_SIZE 0x1000
162  #define FSL_IMX6_PTM1_ADDR 0x0215D000
163  #define FSL_IMX6_PTM1_SIZE 0x1000
164  #define FSL_IMX6_PTM0_ADDR 0x0215C000
165  #define FSL_IMX6_PTM0_SIZE 0x1000
166  #define FSL_IMX6_CTI3_ADDR 0x0215B000
167  #define FSL_IMX6_CTI3_SIZE 0x1000
168  #define FSL_IMX6_CTI2_ADDR 0x0215A000
169  #define FSL_IMX6_CTI2_SIZE 0x1000
170  #define FSL_IMX6_CTI1_ADDR 0x02159000
171  #define FSL_IMX6_CTI1_SIZE 0x1000
172  #define FSL_IMX6_CTI0_ADDR 0x02158000
173  #define FSL_IMX6_CTI0_SIZE 0x1000
174  #define FSL_IMX6_CPU3_PMU_ADDR 0x02157000
175  #define FSL_IMX6_CPU3_PMU_SIZE 0x1000
176  #define FSL_IMX6_CPU3_DEBUG_IF_ADDR 0x02156000
177  #define FSL_IMX6_CPU3_DEBUG_IF_SIZE 0x1000
178  #define FSL_IMX6_CPU2_PMU_ADDR 0x02155000
179  #define FSL_IMX6_CPU2_PMU_SIZE 0x1000
180  #define FSL_IMX6_CPU2_DEBUG_IF_ADDR 0x02154000
181  #define FSL_IMX6_CPU2_DEBUG_IF_SIZE 0x1000
182  #define FSL_IMX6_CPU1_PMU_ADDR 0x02153000
183  #define FSL_IMX6_CPU1_PMU_SIZE 0x1000
184  #define FSL_IMX6_CPU1_DEBUG_IF_ADDR 0x02152000
185  #define FSL_IMX6_CPU1_DEBUG_IF_SIZE 0x1000
186  #define FSL_IMX6_CPU0_PMU_ADDR 0x02151000
187  #define FSL_IMX6_CPU0_PMU_SIZE 0x1000
188  #define FSL_IMX6_CPU0_DEBUG_IF_ADDR 0x02150000
189  #define FSL_IMX6_CPU0_DEBUG_IF_SIZE 0x1000
190  #define FSL_IMX6_CA9_INTEG_ADDR 0x0214F000
191  #define FSL_IMX6_CA9_INTEG_SIZE 0x1000
192  #define FSL_IMX6_FUNNEL_ADDR 0x02144000
193  #define FSL_IMX6_FUNNEL_SIZE 0x1000
194  #define FSL_IMX6_TPIU_ADDR 0x02143000
195  #define FSL_IMX6_TPIU_SIZE 0x1000
196  #define FSL_IMX6_EXT_CTI_ADDR 0x02142000
197  #define FSL_IMX6_EXT_CTI_SIZE 0x1000
198  #define FSL_IMX6_ETB_ADDR 0x02141000
199  #define FSL_IMX6_ETB_SIZE 0x1000
200  #define FSL_IMX6_DAP_ROM_TABLE_ADDR 0x02140000
201  #define FSL_IMX6_DAP_ROM_TABLE_SIZE 0x1000
202  /* DAP end */
203  #define FSL_IMX6_CAAM_ADDR 0x02100000
204  #define FSL_IMX6_CAAM_SIZE 0x10000
205  /* AIPS2 end */
206  #define FSL_IMX6_AIPS_1_ADDR 0x02000000
207  #define FSL_IMX6_AIPS_1_SIZE 0x100000
208  /* AIPS1 */
209  #define FSL_IMX6_SDMA_ADDR 0x020EC000
210  #define FSL_IMX6_SDMA_SIZE 0x4000
211  #define FSL_IMX6_DCIC2_ADDR 0x020E8000
212  #define FSL_IMX6_DCIC2_SIZE 0x4000
213  #define FSL_IMX6_DCIC1_ADDR 0x020E4000
214  #define FSL_IMX6_DCIC1_SIZE 0x4000
215  #define FSL_IMX6_IOMUXC_ADDR 0x020E0000
216  #define FSL_IMX6_IOMUXC_SIZE 0x4000
217  #define FSL_IMX6_PGCARM_ADDR 0x020DCA00
218  #define FSL_IMX6_PGCARM_SIZE 0x20
219  #define FSL_IMX6_PGCPU_ADDR 0x020DC260
220  #define FSL_IMX6_PGCPU_SIZE 0x20
221  #define FSL_IMX6_GPC_ADDR 0x020DC000
222  #define FSL_IMX6_GPC_SIZE 0x4000
223  #define FSL_IMX6_SRC_ADDR 0x020D8000
224  #define FSL_IMX6_SRC_SIZE 0x4000
225  #define FSL_IMX6_EPIT2_ADDR 0x020D4000
226  #define FSL_IMX6_EPIT2_SIZE 0x4000
227  #define FSL_IMX6_EPIT1_ADDR 0x020D0000
228  #define FSL_IMX6_EPIT1_SIZE 0x4000
229  #define FSL_IMX6_SNVSHP_ADDR 0x020CC000
230  #define FSL_IMX6_SNVSHP_SIZE 0x4000
231  #define FSL_IMX6_USBPHY2_ADDR 0x020CA000
232  #define FSL_IMX6_USBPHY2_SIZE 0x1000
233  #define FSL_IMX6_USBPHY1_ADDR 0x020C9000
234  #define FSL_IMX6_USBPHY1_SIZE 0x1000
235  #define FSL_IMX6_ANALOG_ADDR 0x020C8000
236  #define FSL_IMX6_ANALOG_SIZE 0x1000
237  #define FSL_IMX6_CCM_ADDR 0x020C4000
238  #define FSL_IMX6_CCM_SIZE 0x4000
239  #define FSL_IMX6_WDOG2_ADDR 0x020C0000
240  #define FSL_IMX6_WDOG2_SIZE 0x4000
241  #define FSL_IMX6_WDOG1_ADDR 0x020BC000
242  #define FSL_IMX6_WDOG1_SIZE 0x4000
243  #define FSL_IMX6_KPP_ADDR 0x020B8000
244  #define FSL_IMX6_KPP_SIZE 0x4000
245  #define FSL_IMX6_GPIO7_ADDR 0x020B4000
246  #define FSL_IMX6_GPIO7_SIZE 0x4000
247  #define FSL_IMX6_GPIO6_ADDR 0x020B0000
248  #define FSL_IMX6_GPIO6_SIZE 0x4000
249  #define FSL_IMX6_GPIO5_ADDR 0x020AC000
250  #define FSL_IMX6_GPIO5_SIZE 0x4000
251  #define FSL_IMX6_GPIO4_ADDR 0x020A8000
252  #define FSL_IMX6_GPIO4_SIZE 0x4000
253  #define FSL_IMX6_GPIO3_ADDR 0x020A4000
254  #define FSL_IMX6_GPIO3_SIZE 0x4000
255  #define FSL_IMX6_GPIO2_ADDR 0x020A0000
256  #define FSL_IMX6_GPIO2_SIZE 0x4000
257  #define FSL_IMX6_GPIO1_ADDR 0x0209C000
258  #define FSL_IMX6_GPIO1_SIZE 0x4000
259  #define FSL_IMX6_GPT_ADDR 0x02098000
260  #define FSL_IMX6_GPT_SIZE 0x4000
261  #define FSL_IMX6_CAN2_ADDR 0x02094000
262  #define FSL_IMX6_CAN2_SIZE 0x4000
263  #define FSL_IMX6_CAN1_ADDR 0x02090000
264  #define FSL_IMX6_CAN1_SIZE 0x4000
265  #define FSL_IMX6_PWM4_ADDR 0x0208C000
266  #define FSL_IMX6_PWM4_SIZE 0x4000
267  #define FSL_IMX6_PWM3_ADDR 0x02088000
268  #define FSL_IMX6_PWM3_SIZE 0x4000
269  #define FSL_IMX6_PWM2_ADDR 0x02084000
270  #define FSL_IMX6_PWM2_SIZE 0x4000
271  #define FSL_IMX6_PWM1_ADDR 0x02080000
272  #define FSL_IMX6_PWM1_SIZE 0x4000
273  #define FSL_IMX6_AIPS1_CFG_ADDR 0x0207C000
274  #define FSL_IMX6_AIPS1_CFG_SIZE 0x4000
275  #define FSL_IMX6_VPU_ADDR 0x02040000
276  #define FSL_IMX6_VPU_SIZE 0x3C000
277  #define FSL_IMX6_AIPS1_SPBA_ADDR 0x0203C000
278  #define FSL_IMX6_AIPS1_SPBA_SIZE 0x4000
279  #define FSL_IMX6_ASRC_ADDR 0x02034000
280  #define FSL_IMX6_ASRC_SIZE 0x4000
281  #define FSL_IMX6_SSI3_ADDR 0x02030000
282  #define FSL_IMX6_SSI3_SIZE 0x4000
283  #define FSL_IMX6_SSI2_ADDR 0x0202C000
284  #define FSL_IMX6_SSI2_SIZE 0x4000
285  #define FSL_IMX6_SSI1_ADDR 0x02028000
286  #define FSL_IMX6_SSI1_SIZE 0x4000
287  #define FSL_IMX6_ESAI_ADDR 0x02024000
288  #define FSL_IMX6_ESAI_SIZE 0x4000
289  #define FSL_IMX6_UART1_ADDR 0x02020000
290  #define FSL_IMX6_UART1_SIZE 0x4000
291  #define FSL_IMX6_eCSPI5_ADDR 0x02018000
292  #define FSL_IMX6_eCSPI5_SIZE 0x4000
293  #define FSL_IMX6_eCSPI4_ADDR 0x02014000
294  #define FSL_IMX6_eCSPI4_SIZE 0x4000
295  #define FSL_IMX6_eCSPI3_ADDR 0x02010000
296  #define FSL_IMX6_eCSPI3_SIZE 0x4000
297  #define FSL_IMX6_eCSPI2_ADDR 0x0200C000
298  #define FSL_IMX6_eCSPI2_SIZE 0x4000
299  #define FSL_IMX6_eCSPI1_ADDR 0x02008000
300  #define FSL_IMX6_eCSPI1_SIZE 0x4000
301  #define FSL_IMX6_SPDIF_ADDR 0x02004000
302  #define FSL_IMX6_SPDIF_SIZE 0x4000
303  /* AIPS1 end */
304  #define FSL_IMX6_PCIe_REG_ADDR 0x01FFC000
305  #define FSL_IMX6_PCIe_REG_SIZE 0x4000
306  #define FSL_IMX6_PCIe_ADDR 0x01000000
307  #define FSL_IMX6_PCIe_SIZE 0xFFC000
308  #define FSL_IMX6_GPV_1_PL301_CFG_ADDR 0x00C00000
309  #define FSL_IMX6_GPV_1_PL301_CFG_SIZE 0x100000
310  #define FSL_IMX6_GPV_0_PL301_CFG_ADDR 0x00B00000
311  #define FSL_IMX6_GPV_0_PL301_CFG_SIZE 0x100000
312  #define FSL_IMX6_PL310_ADDR 0x00A02000
313  #define FSL_IMX6_PL310_SIZE 0x1000
314  #define FSL_IMX6_A9MPCORE_ADDR 0x00A00000
315  #define FSL_IMX6_A9MPCORE_SIZE 0x2000
316  #define FSL_IMX6_OCRAM_ALIAS_ADDR 0x00940000
317  #define FSL_IMX6_OCRAM_ALIAS_SIZE 0xC0000
318  #define FSL_IMX6_OCRAM_ADDR 0x00900000
319  #define FSL_IMX6_OCRAM_SIZE 0x40000
320  #define FSL_IMX6_GPV_4_PL301_CFG_ADDR 0x00800000
321  #define FSL_IMX6_GPV_4_PL301_CFG_SIZE 0x100000
322  #define FSL_IMX6_GPV_3_PL301_CFG_ADDR 0x00300000
323  #define FSL_IMX6_GPV_3_PL301_CFG_SIZE 0x100000
324  #define FSL_IMX6_GPV_2_PL301_CFG_ADDR 0x00200000
325  #define FSL_IMX6_GPV_2_PL301_CFG_SIZE 0x100000
326  #define FSL_IMX6_DTCP_ADDR 0x00138000
327  #define FSL_IMX6_DTCP_SIZE 0x4000
328  #define FSL_IMX6_GPU_2D_ADDR 0x00134000
329  #define FSL_IMX6_GPU_2D_SIZE 0x4000
330  #define FSL_IMX6_GPU_3D_ADDR 0x00130000
331  #define FSL_IMX6_GPU_3D_SIZE 0x4000
332  #define FSL_IMX6_HDMI_ADDR 0x00120000
333  #define FSL_IMX6_HDMI_SIZE 0x9000
334  #define FSL_IMX6_BCH_ADDR 0x00114000
335  #define FSL_IMX6_BCH_SIZE 0x4000
336  #define FSL_IMX6_GPMI_ADDR 0x00112000
337  #define FSL_IMX6_GPMI_SIZE 0x2000
338  #define FSL_IMX6_APBH_BRIDGE_DMA_ADDR 0x00110000
339  #define FSL_IMX6_APBH_BRIDGE_DMA_SIZE 0x2000
340  #define FSL_IMX6_CAAM_MEM_ADDR 0x00100000
341  #define FSL_IMX6_CAAM_MEM_SIZE 0x4000
342  #define FSL_IMX6_ROM_ADDR 0x00000000
343  #define FSL_IMX6_ROM_SIZE 0x18000
344  
345  #define FSL_IMX6_IOMUXC_IRQ 0
346  #define FSL_IMX6_DAP_IRQ 1
347  #define FSL_IMX6_SDMA_IRQ 2
348  #define FSL_IMX6_VPU_JPEG_IRQ 3
349  #define FSL_IMX6_SNVS_PMIC_IRQ 4
350  #define FSL_IMX6_IPU1_ERROR_IRQ 5
351  #define FSL_IMX6_IPU1_SYNC_IRQ 6
352  #define FSL_IMX6_IPU2_ERROR_IRQ 7
353  #define FSL_IMX6_IPU2_SYNC_IRQ 8
354  #define FSL_IMX6_GPU3D_IRQ 9
355  #define FSL_IMX6_R2D_IRQ 10
356  #define FSL_IMX6_V2D_IRQ 11
357  #define FSL_IMX6_VPU_IRQ 12
358  #define FSL_IMX6_APBH_BRIDGE_DMA_IRQ 13
359  #define FSL_IMX6_EIM_IRQ 14
360  #define FSL_IMX6_BCH_IRQ 15
361  #define FSL_IMX6_GPMI_IRQ 16
362  #define FSL_IMX6_DTCP_IRQ 17
363  #define FSL_IMX6_VDOA_IRQ 18
364  #define FSL_IMX6_SNVS_CONS_IRQ 19
365  #define FSL_IMX6_SNVS_SEC_IRQ 20
366  #define FSL_IMX6_CSU_IRQ 21
367  #define FSL_IMX6_uSDHC1_IRQ 22
368  #define FSL_IMX6_uSDHC2_IRQ 23
369  #define FSL_IMX6_uSDHC3_IRQ 24
370  #define FSL_IMX6_uSDHC4_IRQ 25
371  #define FSL_IMX6_UART1_IRQ 26
372  #define FSL_IMX6_UART2_IRQ 27
373  #define FSL_IMX6_UART3_IRQ 28
374  #define FSL_IMX6_UART4_IRQ 29
375  #define FSL_IMX6_UART5_IRQ 30
376  #define FSL_IMX6_ECSPI1_IRQ 31
377  #define FSL_IMX6_ECSPI2_IRQ 32
378  #define FSL_IMX6_ECSPI3_IRQ 33
379  #define FSL_IMX6_ECSPI4_IRQ 34
380  #define FSL_IMX6_ECSPI5_IRQ 35
381  #define FSL_IMX6_I2C1_IRQ 36
382  #define FSL_IMX6_I2C2_IRQ 37
383  #define FSL_IMX6_I2C3_IRQ 38
384  #define FSL_IMX6_SATA_IRQ 39
385  #define FSL_IMX6_USB_HOST1_IRQ 40
386  #define FSL_IMX6_USB_HOST2_IRQ 41
387  #define FSL_IMX6_USB_HOST3_IRQ 42
388  #define FSL_IMX6_USB_OTG_IRQ 43
389  #define FSL_IMX6_USB_PHY_UTMI0_IRQ 44
390  #define FSL_IMX6_USB_PHY_UTMI1_IRQ 45
391  #define FSL_IMX6_SSI1_IRQ 46
392  #define FSL_IMX6_SSI2_IRQ 47
393  #define FSL_IMX6_SSI3_IRQ 48
394  #define FSL_IMX6_TEMP_IRQ 49
395  #define FSL_IMX6_ASRC_IRQ 50
396  #define FSL_IMX6_ESAI_IRQ 51
397  #define FSL_IMX6_SPDIF_IRQ 52
398  #define FSL_IMX6_MLB150_IRQ 53
399  #define FSL_IMX6_PMU1_IRQ 54
400  #define FSL_IMX6_GPT_IRQ 55
401  #define FSL_IMX6_EPIT1_IRQ 56
402  #define FSL_IMX6_EPIT2_IRQ 57
403  #define FSL_IMX6_GPIO1_INT7_IRQ 58
404  #define FSL_IMX6_GPIO1_INT6_IRQ 59
405  #define FSL_IMX6_GPIO1_INT5_IRQ 60
406  #define FSL_IMX6_GPIO1_INT4_IRQ 61
407  #define FSL_IMX6_GPIO1_INT3_IRQ 62
408  #define FSL_IMX6_GPIO1_INT2_IRQ 63
409  #define FSL_IMX6_GPIO1_INT1_IRQ 64
410  #define FSL_IMX6_GPIO1_INT0_IRQ 65
411  #define FSL_IMX6_GPIO1_LOW_IRQ 66
412  #define FSL_IMX6_GPIO1_HIGH_IRQ 67
413  #define FSL_IMX6_GPIO2_LOW_IRQ 68
414  #define FSL_IMX6_GPIO2_HIGH_IRQ 69
415  #define FSL_IMX6_GPIO3_LOW_IRQ 70
416  #define FSL_IMX6_GPIO3_HIGH_IRQ 71
417  #define FSL_IMX6_GPIO4_LOW_IRQ 72
418  #define FSL_IMX6_GPIO4_HIGH_IRQ 73
419  #define FSL_IMX6_GPIO5_LOW_IRQ 74
420  #define FSL_IMX6_GPIO5_HIGH_IRQ 75
421  #define FSL_IMX6_GPIO6_LOW_IRQ 76
422  #define FSL_IMX6_GPIO6_HIGH_IRQ 77
423  #define FSL_IMX6_GPIO7_LOW_IRQ 78
424  #define FSL_IMX6_GPIO7_HIGH_IRQ 79
425  #define FSL_IMX6_WDOG1_IRQ 80
426  #define FSL_IMX6_WDOG2_IRQ 81
427  #define FSL_IMX6_KPP_IRQ 82
428  #define FSL_IMX6_PWM1_IRQ 83
429  #define FSL_IMX6_PWM2_IRQ 84
430  #define FSL_IMX6_PWM3_IRQ 85
431  #define FSL_IMX6_PWM4_IRQ 86
432  #define FSL_IMX6_CCM1_IRQ 87
433  #define FSL_IMX6_CCM2_IRQ 88
434  #define FSL_IMX6_GPC_IRQ 89
435  #define FSL_IMX6_SRC_IRQ 91
436  #define FSL_IMX6_CPU_L2_IRQ 92
437  #define FSL_IMX6_CPU_PARITY_IRQ 93
438  #define FSL_IMX6_CPU_PERF_IRQ 94
439  #define FSL_IMX6_CPU_CTI_IRQ 95
440  #define FSL_IMX6_SRC_COMB_IRQ 96
441  #define FSL_IMX6_MIPI_CSI1_IRQ 100
442  #define FSL_IMX6_MIPI_CSI2_IRQ 101
443  #define FSL_IMX6_MIPI_DSI_IRQ 102
444  #define FSL_IMX6_MIPI_HSI_IRQ 103
445  #define FSL_IMX6_SJC_IRQ 104
446  #define FSL_IMX6_CAAM0_IRQ 105
447  #define FSL_IMX6_CAAM1_IRQ 106
448  #define FSL_IMX6_ASC1_IRQ 108
449  #define FSL_IMX6_ASC2_IRQ 109
450  #define FSL_IMX6_FLEXCAN1_IRQ 110
451  #define FSL_IMX6_FLEXCAN2_IRQ 111
452  #define FSL_IMX6_HDMI_MASTER_IRQ 115
453  #define FSL_IMX6_HDMI_CEC_IRQ 116
454  #define FSL_IMX6_MLB150_LOW_IRQ 117
455  #define FSL_IMX6_ENET_MAC_IRQ 118
456  #define FSL_IMX6_ENET_MAC_1588_IRQ 119
457  #define FSL_IMX6_PCIE1_IRQ 120
458  #define FSL_IMX6_PCIE2_IRQ 121
459  #define FSL_IMX6_PCIE3_IRQ 122
460  #define FSL_IMX6_PCIE4_IRQ 123
461  #define FSL_IMX6_DCIC1_IRQ 124
462  #define FSL_IMX6_DCIC2_IRQ 125
463  #define FSL_IMX6_MLB150_HIGH_IRQ 126
464  #define FSL_IMX6_PMU2_IRQ 127
465  #define FSL_IMX6_MAX_IRQ 128
466  
467  #endif /* FSL_IMX6_H */
468