1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18 * for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef EXYNOS4210_H 25 #define EXYNOS4210_H 26 27 #include "hw/or-irq.h" 28 #include "hw/sysbus.h" 29 #include "hw/cpu/a9mpcore.h" 30 #include "hw/intc/exynos4210_gic.h" 31 #include "target/arm/cpu-qom.h" 32 #include "qom/object.h" 33 34 #define EXYNOS4210_NCPUS 2 35 36 #define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000 37 #define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000 38 #define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */ 39 40 #define EXYNOS4210_IROM_BASE_ADDR 0x00000000 41 #define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */ 42 #define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000 43 #define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */ 44 45 #define EXYNOS4210_IRAM_BASE_ADDR 0x02020000 46 #define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */ 47 48 /* Secondary CPU startup code is in IROM memory */ 49 #define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADDR 50 #define EXYNOS4210_SMP_BOOT_SIZE 0x1000 51 #define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_ADDR 52 /* Secondary CPU polling address to get loader start from */ 53 #define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814 54 55 #define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000 56 #define EXYNOS4210_L2X0_BASE_ADDR 0x10502000 57 58 /* 59 * exynos4210 IRQ subsystem stub definitions. 60 */ 61 #define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */ 62 63 #define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ 64 64 #define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ 16 65 #define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ \ 66 (EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8) 67 #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ 68 (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) 69 70 #define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit)) 71 #define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) 72 #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ 73 ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) 74 75 /* IRQs number for external and internal GIC */ 76 #define EXYNOS4210_EXT_GIC_NIRQ (160-32) 77 #define EXYNOS4210_INT_GIC_NIRQ 64 78 79 #define EXYNOS4210_I2C_NUMBER 9 80 81 #define EXYNOS4210_NUM_DMA 3 82 83 typedef struct Exynos4210Irq { 84 qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; 85 qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; 86 qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; 87 } Exynos4210Irq; 88 89 struct Exynos4210State { 90 /*< private >*/ 91 SysBusDevice parent_obj; 92 /*< public >*/ 93 ARMCPU *cpu[EXYNOS4210_NCPUS]; 94 Exynos4210Irq irqs; 95 qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; 96 97 MemoryRegion chipid_mem; 98 MemoryRegion iram_mem; 99 MemoryRegion irom_mem; 100 MemoryRegion irom_alias_mem; 101 MemoryRegion boot_secondary; 102 MemoryRegion bootreg_mem; 103 I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; 104 qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; 105 qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; 106 A9MPPrivState a9mpcore; 107 Exynos4210GicState ext_gic; 108 }; 109 110 #define TYPE_EXYNOS4210_SOC "exynos4210" 111 OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC) 112 113 void exynos4210_write_secondary(ARMCPU *cpu, 114 const struct arm_boot_info *info); 115 116 /* Get IRQ number from exynos4210 IRQ subsystem stub. 117 * To identify IRQ source use internal combiner group and bit number 118 * grp - group number 119 * bit - bit number inside group */ 120 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit); 121 122 /* 123 * Get Combiner input GPIO into irqs structure 124 */ 125 void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, 126 int ext); 127 128 /* 129 * exynos4210 UART 130 */ 131 DeviceState *exynos4210_uart_create(hwaddr addr, 132 int fifo_size, 133 int channel, 134 Chardev *chr, 135 qemu_irq irq); 136 137 #endif /* EXYNOS4210_H */ 138