1 /*
2  * BCM2838 peripherals emulation
3  *
4  * Copyright (C) 2022 Ovchinnikov Vitalii <vitalii.ovchinnikov@auriga.com>
5  *
6  * SPDX-License-Identifier: GPL-2.0-or-later
7  */
8 
9 #ifndef BCM2838_PERIPHERALS_H
10 #define BCM2838_PERIPHERALS_H
11 
12 #include "hw/arm/bcm2835_peripherals.h"
13 
14 /* SPI */
15 #define GIC_SPI_INTERRUPT_MBOX         33
16 #define GIC_SPI_INTERRUPT_MPHI         40
17 #define GIC_SPI_INTERRUPT_DWC2         73
18 #define GIC_SPI_INTERRUPT_DMA_0        80
19 #define GIC_SPI_INTERRUPT_DMA_6        86
20 #define GIC_SPI_INTERRUPT_DMA_7_8      87
21 #define GIC_SPI_INTERRUPT_DMA_9_10     88
22 #define GIC_SPI_INTERRUPT_AUX_UART1    93
23 #define GIC_SPI_INTERRUPT_SDHOST       120
24 #define GIC_SPI_INTERRUPT_UART0        121
25 #define GIC_SPI_INTERRUPT_RNG200       125
26 #define GIC_SPI_INTERRUPT_EMMC_EMMC2   126
27 #define GIC_SPI_INTERRUPT_PCI_INT_A    143
28 #define GIC_SPI_INTERRUPT_GENET_A      157
29 #define GIC_SPI_INTERRUPT_GENET_B      158
30 
31 
32 /* GPU (legacy) DMA interrupts */
33 #define GPU_INTERRUPT_DMA0      16
34 #define GPU_INTERRUPT_DMA1      17
35 #define GPU_INTERRUPT_DMA2      18
36 #define GPU_INTERRUPT_DMA3      19
37 #define GPU_INTERRUPT_DMA4      20
38 #define GPU_INTERRUPT_DMA5      21
39 #define GPU_INTERRUPT_DMA6      22
40 #define GPU_INTERRUPT_DMA7_8    23
41 #define GPU_INTERRUPT_DMA9_10   24
42 #define GPU_INTERRUPT_DMA11     25
43 #define GPU_INTERRUPT_DMA12     26
44 #define GPU_INTERRUPT_DMA13     27
45 #define GPU_INTERRUPT_DMA14     28
46 #define GPU_INTERRUPT_DMA15     31
47 
48 #define TYPE_BCM2838_PERIPHERALS "bcm2838-peripherals"
49 OBJECT_DECLARE_TYPE(BCM2838PeripheralState, BCM2838PeripheralClass,
50                     BCM2838_PERIPHERALS)
51 
52 struct BCM2838PeripheralState {
53     /*< private >*/
54     BCMSocPeripheralBaseState parent_obj;
55 
56     /*< public >*/
57     MemoryRegion peri_low_mr;
58     MemoryRegion peri_low_mr_alias;
59     MemoryRegion mphi_mr_alias;
60 
61     OrIRQState mmc_irq_orgate;
62     OrIRQState dma_7_8_irq_orgate;
63     OrIRQState dma_9_10_irq_orgate;
64 };
65 
66 struct BCM2838PeripheralClass {
67     /*< private >*/
68     BCMSocPeripheralBaseClass parent_class;
69     /*< public >*/
70     uint64_t peri_low_size; /* Peripheral lower range size */
71 };
72 
73 #endif /* BCM2838_PERIPHERALS_H */
74