1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/intc/aspeed_vic.h" 17 #include "hw/misc/aspeed_scu.h" 18 #include "hw/misc/aspeed_sdmc.h" 19 #include "hw/misc/aspeed_xdma.h" 20 #include "hw/timer/aspeed_timer.h" 21 #include "hw/timer/aspeed_rtc.h" 22 #include "hw/i2c/aspeed_i2c.h" 23 #include "hw/ssi/aspeed_smc.h" 24 #include "hw/watchdog/wdt_aspeed.h" 25 #include "hw/net/ftgmac100.h" 26 #include "target/arm/cpu.h" 27 #include "hw/gpio/aspeed_gpio.h" 28 #include "hw/sd/aspeed_sdhci.h" 29 30 #define ASPEED_SPIS_NUM 2 31 #define ASPEED_WDTS_NUM 4 32 #define ASPEED_CPUS_NUM 2 33 #define ASPEED_MACS_NUM 4 34 35 typedef struct AspeedSoCState { 36 /*< private >*/ 37 DeviceState parent; 38 39 /*< public >*/ 40 ARMCPU cpu[ASPEED_CPUS_NUM]; 41 uint32_t num_cpus; 42 A15MPPrivState a7mpcore; 43 MemoryRegion sram; 44 AspeedVICState vic; 45 AspeedRtcState rtc; 46 AspeedTimerCtrlState timerctrl; 47 AspeedI2CState i2c; 48 AspeedSCUState scu; 49 AspeedXDMAState xdma; 50 AspeedSMCState fmc; 51 AspeedSMCState spi[ASPEED_SPIS_NUM]; 52 AspeedSDMCState sdmc; 53 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 54 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 55 AspeedMiiState mii[ASPEED_MACS_NUM]; 56 AspeedGPIOState gpio; 57 AspeedGPIOState gpio_1_8v; 58 AspeedSDHCIState sdhci; 59 } AspeedSoCState; 60 61 #define TYPE_ASPEED_SOC "aspeed-soc" 62 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC) 63 64 typedef struct AspeedSoCClass { 65 DeviceClass parent_class; 66 67 const char *name; 68 const char *cpu_type; 69 uint32_t silicon_rev; 70 uint64_t sram_size; 71 int spis_num; 72 int wdts_num; 73 int macs_num; 74 const int *irqmap; 75 const hwaddr *memmap; 76 uint32_t num_cpus; 77 } AspeedSoCClass; 78 79 #define ASPEED_SOC_CLASS(klass) \ 80 OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC) 81 #define ASPEED_SOC_GET_CLASS(obj) \ 82 OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC) 83 84 enum { 85 ASPEED_IOMEM, 86 ASPEED_UART1, 87 ASPEED_UART2, 88 ASPEED_UART3, 89 ASPEED_UART4, 90 ASPEED_UART5, 91 ASPEED_VUART, 92 ASPEED_FMC, 93 ASPEED_SPI1, 94 ASPEED_SPI2, 95 ASPEED_VIC, 96 ASPEED_SDMC, 97 ASPEED_SCU, 98 ASPEED_ADC, 99 ASPEED_VIDEO, 100 ASPEED_SRAM, 101 ASPEED_SDHCI, 102 ASPEED_GPIO, 103 ASPEED_GPIO_1_8V, 104 ASPEED_RTC, 105 ASPEED_TIMER1, 106 ASPEED_TIMER2, 107 ASPEED_TIMER3, 108 ASPEED_TIMER4, 109 ASPEED_TIMER5, 110 ASPEED_TIMER6, 111 ASPEED_TIMER7, 112 ASPEED_TIMER8, 113 ASPEED_WDT, 114 ASPEED_PWM, 115 ASPEED_LPC, 116 ASPEED_IBT, 117 ASPEED_I2C, 118 ASPEED_ETH1, 119 ASPEED_ETH2, 120 ASPEED_ETH3, 121 ASPEED_ETH4, 122 ASPEED_MII1, 123 ASPEED_MII2, 124 ASPEED_MII3, 125 ASPEED_MII4, 126 ASPEED_SDRAM, 127 ASPEED_XDMA, 128 }; 129 130 #endif /* ASPEED_SOC_H */ 131