1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/misc/aspeed_scu.h" 19 #include "hw/adc/aspeed_adc.h" 20 #include "hw/misc/aspeed_sdmc.h" 21 #include "hw/misc/aspeed_xdma.h" 22 #include "hw/timer/aspeed_timer.h" 23 #include "hw/rtc/aspeed_rtc.h" 24 #include "hw/i2c/aspeed_i2c.h" 25 #include "hw/misc/aspeed_i3c.h" 26 #include "hw/ssi/aspeed_smc.h" 27 #include "hw/misc/aspeed_hace.h" 28 #include "hw/misc/aspeed_sbc.h" 29 #include "hw/watchdog/wdt_aspeed.h" 30 #include "hw/net/ftgmac100.h" 31 #include "target/arm/cpu.h" 32 #include "hw/gpio/aspeed_gpio.h" 33 #include "hw/sd/aspeed_sdhci.h" 34 #include "hw/usb/hcd-ehci.h" 35 #include "qom/object.h" 36 #include "hw/misc/aspeed_lpc.h" 37 #include "hw/misc/unimp.h" 38 39 #define ASPEED_SPIS_NUM 2 40 #define ASPEED_EHCIS_NUM 2 41 #define ASPEED_WDTS_NUM 4 42 #define ASPEED_CPUS_NUM 2 43 #define ASPEED_MACS_NUM 4 44 45 struct AspeedSoCState { 46 /*< private >*/ 47 DeviceState parent; 48 49 /*< public >*/ 50 ARMCPU cpu[ASPEED_CPUS_NUM]; 51 A15MPPrivState a7mpcore; 52 ARMv7MState armv7m; 53 MemoryRegion *memory; 54 MemoryRegion *dram_mr; 55 MemoryRegion dram_container; 56 MemoryRegion sram; 57 AspeedVICState vic; 58 AspeedRtcState rtc; 59 AspeedTimerCtrlState timerctrl; 60 AspeedI2CState i2c; 61 AspeedI3CState i3c; 62 AspeedSCUState scu; 63 AspeedHACEState hace; 64 AspeedXDMAState xdma; 65 AspeedADCState adc; 66 AspeedSMCState fmc; 67 AspeedSMCState spi[ASPEED_SPIS_NUM]; 68 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 69 AspeedSBCState sbc; 70 UnimplementedDeviceState sbc_unimplemented; 71 AspeedSDMCState sdmc; 72 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 73 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 74 AspeedMiiState mii[ASPEED_MACS_NUM]; 75 AspeedGPIOState gpio; 76 AspeedGPIOState gpio_1_8v; 77 AspeedSDHCIState sdhci; 78 AspeedSDHCIState emmc; 79 AspeedLPCState lpc; 80 uint32_t uart_default; 81 Clock *sysclk; 82 UnimplementedDeviceState iomem; 83 UnimplementedDeviceState video; 84 UnimplementedDeviceState emmc_boot_controller; 85 UnimplementedDeviceState dpmcu; 86 }; 87 88 #define TYPE_ASPEED_SOC "aspeed-soc" 89 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 90 91 struct AspeedSoCClass { 92 DeviceClass parent_class; 93 94 const char *name; 95 const char *cpu_type; 96 uint32_t silicon_rev; 97 uint64_t sram_size; 98 int spis_num; 99 int ehcis_num; 100 int wdts_num; 101 int macs_num; 102 int uarts_num; 103 const int *irqmap; 104 const hwaddr *memmap; 105 uint32_t num_cpus; 106 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 107 }; 108 109 110 enum { 111 ASPEED_DEV_IOMEM, 112 ASPEED_DEV_UART1, 113 ASPEED_DEV_UART2, 114 ASPEED_DEV_UART3, 115 ASPEED_DEV_UART4, 116 ASPEED_DEV_UART5, 117 ASPEED_DEV_UART6, 118 ASPEED_DEV_UART7, 119 ASPEED_DEV_UART8, 120 ASPEED_DEV_UART9, 121 ASPEED_DEV_UART10, 122 ASPEED_DEV_UART11, 123 ASPEED_DEV_UART12, 124 ASPEED_DEV_UART13, 125 ASPEED_DEV_VUART, 126 ASPEED_DEV_FMC, 127 ASPEED_DEV_SPI1, 128 ASPEED_DEV_SPI2, 129 ASPEED_DEV_EHCI1, 130 ASPEED_DEV_EHCI2, 131 ASPEED_DEV_VIC, 132 ASPEED_DEV_SDMC, 133 ASPEED_DEV_SCU, 134 ASPEED_DEV_ADC, 135 ASPEED_DEV_SBC, 136 ASPEED_DEV_EMMC_BC, 137 ASPEED_DEV_VIDEO, 138 ASPEED_DEV_SRAM, 139 ASPEED_DEV_SDHCI, 140 ASPEED_DEV_GPIO, 141 ASPEED_DEV_GPIO_1_8V, 142 ASPEED_DEV_RTC, 143 ASPEED_DEV_TIMER1, 144 ASPEED_DEV_TIMER2, 145 ASPEED_DEV_TIMER3, 146 ASPEED_DEV_TIMER4, 147 ASPEED_DEV_TIMER5, 148 ASPEED_DEV_TIMER6, 149 ASPEED_DEV_TIMER7, 150 ASPEED_DEV_TIMER8, 151 ASPEED_DEV_WDT, 152 ASPEED_DEV_PWM, 153 ASPEED_DEV_LPC, 154 ASPEED_DEV_IBT, 155 ASPEED_DEV_I2C, 156 ASPEED_DEV_ETH1, 157 ASPEED_DEV_ETH2, 158 ASPEED_DEV_ETH3, 159 ASPEED_DEV_ETH4, 160 ASPEED_DEV_MII1, 161 ASPEED_DEV_MII2, 162 ASPEED_DEV_MII3, 163 ASPEED_DEV_MII4, 164 ASPEED_DEV_SDRAM, 165 ASPEED_DEV_XDMA, 166 ASPEED_DEV_EMMC, 167 ASPEED_DEV_KCS, 168 ASPEED_DEV_HACE, 169 ASPEED_DEV_DPMCU, 170 ASPEED_DEV_DP, 171 ASPEED_DEV_I3C, 172 }; 173 174 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 175 void aspeed_soc_uart_init(AspeedSoCState *s); 176 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 177 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 178 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 179 const char *name, hwaddr addr, 180 uint64_t size); 181 182 #endif /* ASPEED_SOC_H */ 183