1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/intc/aspeed_vic.h" 17 #include "hw/misc/aspeed_scu.h" 18 #include "hw/misc/aspeed_sdmc.h" 19 #include "hw/misc/aspeed_xdma.h" 20 #include "hw/timer/aspeed_timer.h" 21 #include "hw/rtc/aspeed_rtc.h" 22 #include "hw/i2c/aspeed_i2c.h" 23 #include "hw/ssi/aspeed_smc.h" 24 #include "hw/watchdog/wdt_aspeed.h" 25 #include "hw/net/ftgmac100.h" 26 #include "target/arm/cpu.h" 27 #include "hw/gpio/aspeed_gpio.h" 28 #include "hw/sd/aspeed_sdhci.h" 29 #include "hw/usb/hcd-ehci.h" 30 #include "qom/object.h" 31 #include "hw/misc/aspeed_lpc.h" 32 33 #define ASPEED_SPIS_NUM 2 34 #define ASPEED_EHCIS_NUM 2 35 #define ASPEED_WDTS_NUM 4 36 #define ASPEED_CPUS_NUM 2 37 #define ASPEED_MACS_NUM 4 38 39 struct AspeedSoCState { 40 /*< private >*/ 41 DeviceState parent; 42 43 /*< public >*/ 44 ARMCPU cpu[ASPEED_CPUS_NUM]; 45 A15MPPrivState a7mpcore; 46 MemoryRegion *dram_mr; 47 MemoryRegion sram; 48 AspeedVICState vic; 49 AspeedRtcState rtc; 50 AspeedTimerCtrlState timerctrl; 51 AspeedI2CState i2c; 52 AspeedSCUState scu; 53 AspeedXDMAState xdma; 54 AspeedSMCState fmc; 55 AspeedSMCState spi[ASPEED_SPIS_NUM]; 56 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 57 AspeedSDMCState sdmc; 58 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 59 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 60 AspeedMiiState mii[ASPEED_MACS_NUM]; 61 AspeedGPIOState gpio; 62 AspeedGPIOState gpio_1_8v; 63 AspeedSDHCIState sdhci; 64 AspeedSDHCIState emmc; 65 AspeedLPCState lpc; 66 }; 67 68 #define TYPE_ASPEED_SOC "aspeed-soc" 69 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 70 71 struct AspeedSoCClass { 72 DeviceClass parent_class; 73 74 const char *name; 75 const char *cpu_type; 76 uint32_t silicon_rev; 77 uint64_t sram_size; 78 int spis_num; 79 int ehcis_num; 80 int wdts_num; 81 int macs_num; 82 const int *irqmap; 83 const hwaddr *memmap; 84 uint32_t num_cpus; 85 }; 86 87 88 enum { 89 ASPEED_DEV_IOMEM, 90 ASPEED_DEV_UART1, 91 ASPEED_DEV_UART2, 92 ASPEED_DEV_UART3, 93 ASPEED_DEV_UART4, 94 ASPEED_DEV_UART5, 95 ASPEED_DEV_VUART, 96 ASPEED_DEV_FMC, 97 ASPEED_DEV_SPI1, 98 ASPEED_DEV_SPI2, 99 ASPEED_DEV_EHCI1, 100 ASPEED_DEV_EHCI2, 101 ASPEED_DEV_VIC, 102 ASPEED_DEV_SDMC, 103 ASPEED_DEV_SCU, 104 ASPEED_DEV_ADC, 105 ASPEED_DEV_VIDEO, 106 ASPEED_DEV_SRAM, 107 ASPEED_DEV_SDHCI, 108 ASPEED_DEV_GPIO, 109 ASPEED_DEV_GPIO_1_8V, 110 ASPEED_DEV_RTC, 111 ASPEED_DEV_TIMER1, 112 ASPEED_DEV_TIMER2, 113 ASPEED_DEV_TIMER3, 114 ASPEED_DEV_TIMER4, 115 ASPEED_DEV_TIMER5, 116 ASPEED_DEV_TIMER6, 117 ASPEED_DEV_TIMER7, 118 ASPEED_DEV_TIMER8, 119 ASPEED_DEV_WDT, 120 ASPEED_DEV_PWM, 121 ASPEED_DEV_LPC, 122 ASPEED_DEV_IBT, 123 ASPEED_DEV_I2C, 124 ASPEED_DEV_ETH1, 125 ASPEED_DEV_ETH2, 126 ASPEED_DEV_ETH3, 127 ASPEED_DEV_ETH4, 128 ASPEED_DEV_MII1, 129 ASPEED_DEV_MII2, 130 ASPEED_DEV_MII3, 131 ASPEED_DEV_MII4, 132 ASPEED_DEV_SDRAM, 133 ASPEED_DEV_XDMA, 134 ASPEED_DEV_EMMC, 135 ASPEED_DEV_KCS, 136 }; 137 138 #endif /* ASPEED_SOC_H */ 139