1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/intc/aspeed_intc.h" 19 #include "hw/misc/aspeed_scu.h" 20 #include "hw/adc/aspeed_adc.h" 21 #include "hw/misc/aspeed_gfx.h" 22 #include "hw/misc/aspeed_sdmc.h" 23 #include "hw/misc/aspeed_xdma.h" 24 #include "hw/timer/aspeed_timer.h" 25 #include "hw/rtc/aspeed_rtc.h" 26 #include "hw/misc/aspeed_ibt.h" 27 #include "hw/i2c/aspeed_i2c.h" 28 #include "hw/i3c/aspeed_i3c.h" 29 #include "hw/ssi/aspeed_smc.h" 30 #include "hw/misc/aspeed_hace.h" 31 #include "hw/misc/aspeed_sbc.h" 32 #include "hw/misc/aspeed_sli.h" 33 #include "hw/misc/aspeed_pwm.h" 34 #include "hw/watchdog/wdt_aspeed.h" 35 #include "hw/net/ftgmac100.h" 36 #include "target/arm/cpu.h" 37 #include "hw/gpio/aspeed_gpio.h" 38 #include "hw/sd/aspeed_sdhci.h" 39 #include "hw/usb/hcd-ehci.h" 40 #include "hw/usb/hcd-uhci-sysbus.h" 41 #include "qom/object.h" 42 #include "hw/misc/aspeed_lpc.h" 43 #include "hw/misc/unimp.h" 44 #include "hw/pci-host/aspeed_pcie.h" 45 #include "hw/misc/aspeed_peci.h" 46 #include "hw/fsi/aspeed_apb2opb.h" 47 #include "hw/char/serial-mm.h" 48 #include "hw/intc/arm_gicv3.h" 49 50 #define ASPEED_SPIS_NUM 2 51 #define ASPEED_EHCIS_NUM 2 52 #define ASPEED_WDTS_NUM 8 53 #define ASPEED_CPUS_NUM 4 54 #define ASPEED_MACS_NUM 4 55 #define ASPEED_UARTS_NUM 13 56 #define ASPEED_JTAG_NUM 2 57 58 struct AspeedSoCState { 59 DeviceState parent; 60 61 MemoryRegion *memory; 62 MemoryRegion *dram_mr; 63 MemoryRegion dram_container; 64 MemoryRegion sram; 65 MemoryRegion spi_boot_container; 66 MemoryRegion spi_boot; 67 AddressSpace dram_as; 68 AspeedRtcState rtc; 69 AspeedTimerCtrlState timerctrl; 70 AspeedIBTState ibt; 71 AspeedI2CState i2c; 72 AspeedI3CState i3c; 73 AspeedSCUState scu; 74 AspeedSCUState scuio; 75 AspeedHACEState hace; 76 AspeedXDMAState xdma; 77 AspeedADCState adc; 78 AspeedSMCState fmc; 79 AspeedSMCState spi[ASPEED_SPIS_NUM]; 80 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 81 ASPEEDUHCIState uhci; 82 AspeedSBCState sbc; 83 AspeedSLIState sli; 84 AspeedSLIState sliio; 85 MemoryRegion secsram; 86 UnimplementedDeviceState sbc_unimplemented; 87 AspeedSDMCState sdmc; 88 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 89 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 90 AspeedMiiState mii[ASPEED_MACS_NUM]; 91 AspeedGPIOState gpio; 92 AspeedGPIOState gpio_1_8v; 93 AspeedSDHCIState sdhci; 94 AspeedSDHCIState emmc; 95 AspeedLPCState lpc; 96 AspeedPCIECfg pcie; 97 AspeedPCIEPhy pcie_phy[2]; 98 AspeedPECIState peci; 99 AspeedGFXState gfx; 100 SerialMM uart[ASPEED_UARTS_NUM]; 101 Clock *sysclk; 102 UnimplementedDeviceState iomem; 103 UnimplementedDeviceState video; 104 UnimplementedDeviceState emmc_boot_controller; 105 UnimplementedDeviceState dpmcu; 106 AspeedPWMState pwm; 107 UnimplementedDeviceState espi; 108 UnimplementedDeviceState udc; 109 UnimplementedDeviceState sgpiom; 110 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; 111 AspeedAPB2OPBState fsi[2]; 112 }; 113 114 #define TYPE_ASPEED_SOC "aspeed-soc" 115 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 116 117 struct Aspeed2400SoCState { 118 AspeedSoCState parent; 119 120 ARMCPU cpu[ASPEED_CPUS_NUM]; 121 AspeedVICState vic; 122 }; 123 124 #define TYPE_ASPEED2400_SOC "aspeed2400-soc" 125 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) 126 127 struct Aspeed2600SoCState { 128 AspeedSoCState parent; 129 130 A15MPPrivState a7mpcore; 131 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */ 132 }; 133 134 #define TYPE_ASPEED2600_SOC "aspeed2600-soc" 135 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) 136 137 struct Aspeed27x0SoCState { 138 AspeedSoCState parent; 139 140 ARMCPU cpu[ASPEED_CPUS_NUM]; 141 AspeedINTCState intc; 142 GICv3State gic; 143 MemoryRegion dram_empty; 144 }; 145 146 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc" 147 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC) 148 149 struct Aspeed10x0SoCState { 150 AspeedSoCState parent; 151 152 ARMv7MState armv7m; 153 }; 154 155 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" 156 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) 157 158 struct AspeedSoCClass { 159 DeviceClass parent_class; 160 161 const char *name; 162 /** valid_cpu_types: NULL terminated array of a single CPU type. */ 163 const char * const *valid_cpu_types; 164 uint32_t silicon_rev; 165 uint64_t sram_size; 166 uint64_t secsram_size; 167 int spis_num; 168 int ehcis_num; 169 int wdts_num; 170 int macs_num; 171 int uarts_num; 172 int uarts_base; 173 const int *irqmap; 174 const hwaddr *memmap; 175 uint32_t num_cpus; 176 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 177 bool (*boot_from_emmc)(AspeedSoCState *s); 178 }; 179 180 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); 181 182 enum { 183 ASPEED_DEV_SPI_BOOT, 184 ASPEED_DEV_IOMEM, 185 ASPEED_DEV_UART0, 186 ASPEED_DEV_UART1, 187 ASPEED_DEV_UART2, 188 ASPEED_DEV_UART3, 189 ASPEED_DEV_UART4, 190 ASPEED_DEV_UART5, 191 ASPEED_DEV_UART6, 192 ASPEED_DEV_UART7, 193 ASPEED_DEV_UART8, 194 ASPEED_DEV_UART9, 195 ASPEED_DEV_UART10, 196 ASPEED_DEV_UART11, 197 ASPEED_DEV_UART12, 198 ASPEED_DEV_UART13, 199 ASPEED_DEV_VUART, 200 ASPEED_DEV_FMC, 201 ASPEED_DEV_SPI0, 202 ASPEED_DEV_SPI1, 203 ASPEED_DEV_SPI2, 204 ASPEED_DEV_EHCI1, 205 ASPEED_DEV_EHCI2, 206 ASPEED_DEV_UHCI, 207 ASPEED_DEV_VIC, 208 ASPEED_DEV_INTC, 209 ASPEED_DEV_SDMC, 210 ASPEED_DEV_SCU, 211 ASPEED_DEV_ADC, 212 ASPEED_DEV_SBC, 213 ASPEED_DEV_SECSRAM, 214 ASPEED_DEV_EMMC_BC, 215 ASPEED_DEV_VIDEO, 216 ASPEED_DEV_SRAM, 217 ASPEED_DEV_SDHCI, 218 ASPEED_DEV_GPIO, 219 ASPEED_DEV_GPIO_1_8V, 220 ASPEED_DEV_RTC, 221 ASPEED_DEV_TIMER1, 222 ASPEED_DEV_TIMER2, 223 ASPEED_DEV_TIMER3, 224 ASPEED_DEV_TIMER4, 225 ASPEED_DEV_TIMER5, 226 ASPEED_DEV_TIMER6, 227 ASPEED_DEV_TIMER7, 228 ASPEED_DEV_TIMER8, 229 ASPEED_DEV_WDT, 230 ASPEED_DEV_PWM, 231 ASPEED_DEV_LPC, 232 ASPEED_DEV_IBT, 233 ASPEED_DEV_I2C, 234 ASPEED_DEV_PCIE_PHY1, 235 ASPEED_DEV_PCIE_PHY2, 236 ASPEED_DEV_PCIE, 237 ASPEED_DEV_PCIE_MMIO1, 238 ASPEED_DEV_PCIE_MMIO2, 239 ASPEED_DEV_PECI, 240 ASPEED_DEV_ETH1, 241 ASPEED_DEV_ETH2, 242 ASPEED_DEV_ETH3, 243 ASPEED_DEV_ETH4, 244 ASPEED_DEV_MII1, 245 ASPEED_DEV_MII2, 246 ASPEED_DEV_MII3, 247 ASPEED_DEV_MII4, 248 ASPEED_DEV_SDRAM, 249 ASPEED_DEV_XDMA, 250 ASPEED_DEV_EMMC, 251 ASPEED_DEV_KCS, 252 ASPEED_DEV_HACE, 253 ASPEED_DEV_GFX, 254 ASPEED_DEV_DPMCU, 255 ASPEED_DEV_DP, 256 ASPEED_DEV_I3C, 257 ASPEED_DEV_ESPI, 258 ASPEED_DEV_UDC, 259 ASPEED_DEV_SGPIOM, 260 ASPEED_DEV_JTAG0, 261 ASPEED_DEV_JTAG1, 262 ASPEED_DEV_FSI1, 263 ASPEED_DEV_FSI2, 264 ASPEED_DEV_SCUIO, 265 ASPEED_DEV_SLI, 266 ASPEED_DEV_SLIIO, 267 ASPEED_GIC_DIST, 268 ASPEED_GIC_REDIST, 269 }; 270 271 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 272 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); 273 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); 274 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 275 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 276 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 277 const char *name, hwaddr addr, 278 uint64_t size); 279 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 280 unsigned int count, int unit0); 281 282 static inline int aspeed_uart_index(int uart_dev) 283 { 284 return uart_dev - ASPEED_DEV_UART0; 285 } 286 287 static inline int aspeed_uart_first(AspeedSoCClass *sc) 288 { 289 return aspeed_uart_index(sc->uarts_base); 290 } 291 292 static inline int aspeed_uart_last(AspeedSoCClass *sc) 293 { 294 return aspeed_uart_first(sc) + sc->uarts_num - 1; 295 } 296 297 #endif /* ASPEED_SOC_H */ 298