1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/misc/aspeed_scu.h" 19 #include "hw/adc/aspeed_adc.h" 20 #include "hw/misc/aspeed_sdmc.h" 21 #include "hw/misc/aspeed_xdma.h" 22 #include "hw/timer/aspeed_timer.h" 23 #include "hw/rtc/aspeed_rtc.h" 24 #include "hw/i2c/aspeed_i2c.h" 25 #include "hw/misc/aspeed_i3c.h" 26 #include "hw/ssi/aspeed_smc.h" 27 #include "hw/misc/aspeed_hace.h" 28 #include "hw/misc/aspeed_sbc.h" 29 #include "hw/watchdog/wdt_aspeed.h" 30 #include "hw/net/ftgmac100.h" 31 #include "target/arm/cpu.h" 32 #include "hw/gpio/aspeed_gpio.h" 33 #include "hw/sd/aspeed_sdhci.h" 34 #include "hw/usb/hcd-ehci.h" 35 #include "qom/object.h" 36 #include "hw/misc/aspeed_lpc.h" 37 #include "hw/misc/unimp.h" 38 #include "hw/misc/aspeed_peci.h" 39 #include "hw/char/serial.h" 40 41 #define ASPEED_SPIS_NUM 2 42 #define ASPEED_EHCIS_NUM 2 43 #define ASPEED_WDTS_NUM 4 44 #define ASPEED_CPUS_NUM 2 45 #define ASPEED_MACS_NUM 4 46 #define ASPEED_UARTS_NUM 13 47 #define ASPEED_JTAG_NUM 2 48 49 struct AspeedSoCState { 50 /*< private >*/ 51 DeviceState parent; 52 53 /*< public >*/ 54 ARMCPU cpu[ASPEED_CPUS_NUM]; 55 A15MPPrivState a7mpcore; 56 ARMv7MState armv7m; 57 MemoryRegion *memory; 58 MemoryRegion *dram_mr; 59 MemoryRegion dram_container; 60 MemoryRegion sram; 61 AspeedVICState vic; 62 AspeedRtcState rtc; 63 AspeedTimerCtrlState timerctrl; 64 AspeedI2CState i2c; 65 AspeedI3CState i3c; 66 AspeedSCUState scu; 67 AspeedHACEState hace; 68 AspeedXDMAState xdma; 69 AspeedADCState adc; 70 AspeedSMCState fmc; 71 AspeedSMCState spi[ASPEED_SPIS_NUM]; 72 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 73 AspeedSBCState sbc; 74 MemoryRegion secsram; 75 UnimplementedDeviceState sbc_unimplemented; 76 AspeedSDMCState sdmc; 77 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 78 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 79 AspeedMiiState mii[ASPEED_MACS_NUM]; 80 AspeedGPIOState gpio; 81 AspeedGPIOState gpio_1_8v; 82 AspeedSDHCIState sdhci; 83 AspeedSDHCIState emmc; 84 AspeedLPCState lpc; 85 AspeedPECIState peci; 86 SerialMM uart[ASPEED_UARTS_NUM]; 87 Clock *sysclk; 88 UnimplementedDeviceState iomem; 89 UnimplementedDeviceState video; 90 UnimplementedDeviceState emmc_boot_controller; 91 UnimplementedDeviceState dpmcu; 92 UnimplementedDeviceState pwm; 93 UnimplementedDeviceState espi; 94 UnimplementedDeviceState udc; 95 UnimplementedDeviceState sgpiom; 96 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; 97 }; 98 99 #define TYPE_ASPEED_SOC "aspeed-soc" 100 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 101 102 struct AspeedSoCClass { 103 DeviceClass parent_class; 104 105 const char *name; 106 const char *cpu_type; 107 uint32_t silicon_rev; 108 uint64_t sram_size; 109 uint64_t secsram_size; 110 int spis_num; 111 int ehcis_num; 112 int wdts_num; 113 int macs_num; 114 int uarts_num; 115 const int *irqmap; 116 const hwaddr *memmap; 117 uint32_t num_cpus; 118 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 119 }; 120 121 122 enum { 123 ASPEED_DEV_IOMEM, 124 ASPEED_DEV_UART1, 125 ASPEED_DEV_UART2, 126 ASPEED_DEV_UART3, 127 ASPEED_DEV_UART4, 128 ASPEED_DEV_UART5, 129 ASPEED_DEV_UART6, 130 ASPEED_DEV_UART7, 131 ASPEED_DEV_UART8, 132 ASPEED_DEV_UART9, 133 ASPEED_DEV_UART10, 134 ASPEED_DEV_UART11, 135 ASPEED_DEV_UART12, 136 ASPEED_DEV_UART13, 137 ASPEED_DEV_VUART, 138 ASPEED_DEV_FMC, 139 ASPEED_DEV_SPI1, 140 ASPEED_DEV_SPI2, 141 ASPEED_DEV_EHCI1, 142 ASPEED_DEV_EHCI2, 143 ASPEED_DEV_VIC, 144 ASPEED_DEV_SDMC, 145 ASPEED_DEV_SCU, 146 ASPEED_DEV_ADC, 147 ASPEED_DEV_SBC, 148 ASPEED_DEV_SECSRAM, 149 ASPEED_DEV_EMMC_BC, 150 ASPEED_DEV_VIDEO, 151 ASPEED_DEV_SRAM, 152 ASPEED_DEV_SDHCI, 153 ASPEED_DEV_GPIO, 154 ASPEED_DEV_GPIO_1_8V, 155 ASPEED_DEV_RTC, 156 ASPEED_DEV_TIMER1, 157 ASPEED_DEV_TIMER2, 158 ASPEED_DEV_TIMER3, 159 ASPEED_DEV_TIMER4, 160 ASPEED_DEV_TIMER5, 161 ASPEED_DEV_TIMER6, 162 ASPEED_DEV_TIMER7, 163 ASPEED_DEV_TIMER8, 164 ASPEED_DEV_WDT, 165 ASPEED_DEV_PWM, 166 ASPEED_DEV_LPC, 167 ASPEED_DEV_IBT, 168 ASPEED_DEV_I2C, 169 ASPEED_DEV_PECI, 170 ASPEED_DEV_ETH1, 171 ASPEED_DEV_ETH2, 172 ASPEED_DEV_ETH3, 173 ASPEED_DEV_ETH4, 174 ASPEED_DEV_MII1, 175 ASPEED_DEV_MII2, 176 ASPEED_DEV_MII3, 177 ASPEED_DEV_MII4, 178 ASPEED_DEV_SDRAM, 179 ASPEED_DEV_XDMA, 180 ASPEED_DEV_EMMC, 181 ASPEED_DEV_KCS, 182 ASPEED_DEV_HACE, 183 ASPEED_DEV_DPMCU, 184 ASPEED_DEV_DP, 185 ASPEED_DEV_I3C, 186 ASPEED_DEV_ESPI, 187 ASPEED_DEV_UDC, 188 ASPEED_DEV_SGPIOM, 189 ASPEED_DEV_JTAG0, 190 ASPEED_DEV_JTAG1, 191 }; 192 193 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 194 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); 195 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); 196 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 197 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 198 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 199 const char *name, hwaddr addr, 200 uint64_t size); 201 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 202 unsigned int count, int unit0); 203 204 #endif /* ASPEED_SOC_H */ 205