1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/intc/aspeed_intc.h" 19 #include "hw/misc/aspeed_scu.h" 20 #include "hw/adc/aspeed_adc.h" 21 #include "hw/misc/aspeed_sdmc.h" 22 #include "hw/misc/aspeed_xdma.h" 23 #include "hw/timer/aspeed_timer.h" 24 #include "hw/rtc/aspeed_rtc.h" 25 #include "hw/i2c/aspeed_i2c.h" 26 #include "hw/misc/aspeed_i3c.h" 27 #include "hw/ssi/aspeed_smc.h" 28 #include "hw/misc/aspeed_hace.h" 29 #include "hw/misc/aspeed_sbc.h" 30 #include "hw/misc/aspeed_sli.h" 31 #include "hw/watchdog/wdt_aspeed.h" 32 #include "hw/net/ftgmac100.h" 33 #include "target/arm/cpu.h" 34 #include "hw/gpio/aspeed_gpio.h" 35 #include "hw/sd/aspeed_sdhci.h" 36 #include "hw/usb/hcd-ehci.h" 37 #include "qom/object.h" 38 #include "hw/misc/aspeed_lpc.h" 39 #include "hw/misc/unimp.h" 40 #include "hw/misc/aspeed_peci.h" 41 #include "hw/fsi/aspeed_apb2opb.h" 42 #include "hw/char/serial-mm.h" 43 #include "hw/intc/arm_gicv3.h" 44 45 #define ASPEED_SPIS_NUM 3 46 #define ASPEED_EHCIS_NUM 4 47 #define ASPEED_WDTS_NUM 8 48 #define ASPEED_CPUS_NUM 4 49 #define ASPEED_MACS_NUM 4 50 #define ASPEED_UARTS_NUM 13 51 #define ASPEED_JTAG_NUM 2 52 53 struct AspeedSoCState { 54 DeviceState parent; 55 56 MemoryRegion *memory; 57 MemoryRegion *dram_mr; 58 MemoryRegion dram_container; 59 MemoryRegion sram; 60 MemoryRegion spi_boot_container; 61 MemoryRegion spi_boot; 62 MemoryRegion vbootrom; 63 AddressSpace dram_as; 64 AspeedRtcState rtc; 65 AspeedTimerCtrlState timerctrl; 66 AspeedI2CState i2c; 67 AspeedI3CState i3c; 68 AspeedSCUState scu; 69 AspeedSCUState scuio; 70 AspeedHACEState hace; 71 AspeedXDMAState xdma; 72 AspeedADCState adc; 73 AspeedSMCState fmc; 74 AspeedSMCState spi[ASPEED_SPIS_NUM]; 75 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 76 AspeedSBCState sbc; 77 AspeedSLIState sli; 78 AspeedSLIState sliio; 79 MemoryRegion secsram; 80 UnimplementedDeviceState sbc_unimplemented; 81 AspeedSDMCState sdmc; 82 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 83 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 84 AspeedMiiState mii[ASPEED_MACS_NUM]; 85 AspeedGPIOState gpio; 86 AspeedGPIOState gpio_1_8v; 87 AspeedSDHCIState sdhci; 88 AspeedSDHCIState emmc; 89 AspeedLPCState lpc; 90 AspeedPECIState peci; 91 SerialMM uart[ASPEED_UARTS_NUM]; 92 Clock *sysclk; 93 UnimplementedDeviceState iomem; 94 UnimplementedDeviceState iomem0; 95 UnimplementedDeviceState iomem1; 96 UnimplementedDeviceState video; 97 UnimplementedDeviceState emmc_boot_controller; 98 UnimplementedDeviceState dpmcu; 99 UnimplementedDeviceState pwm; 100 UnimplementedDeviceState espi; 101 UnimplementedDeviceState udc; 102 UnimplementedDeviceState sgpiom; 103 UnimplementedDeviceState ltpi; 104 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; 105 AspeedAPB2OPBState fsi[2]; 106 }; 107 108 #define TYPE_ASPEED_SOC "aspeed-soc" 109 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 110 111 struct Aspeed2400SoCState { 112 AspeedSoCState parent; 113 114 ARMCPU cpu[ASPEED_CPUS_NUM]; 115 AspeedVICState vic; 116 }; 117 118 #define TYPE_ASPEED2400_SOC "aspeed2400-soc" 119 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) 120 121 struct Aspeed2600SoCState { 122 AspeedSoCState parent; 123 124 A15MPPrivState a7mpcore; 125 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */ 126 }; 127 128 #define TYPE_ASPEED2600_SOC "aspeed2600-soc" 129 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) 130 131 struct Aspeed27x0SoCState { 132 AspeedSoCState parent; 133 134 ARMCPU cpu[ASPEED_CPUS_NUM]; 135 AspeedINTCState intc[2]; 136 GICv3State gic; 137 MemoryRegion dram_empty; 138 }; 139 140 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc" 141 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC) 142 143 struct Aspeed10x0SoCState { 144 AspeedSoCState parent; 145 146 ARMv7MState armv7m; 147 }; 148 149 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" 150 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) 151 152 struct AspeedSoCClass { 153 DeviceClass parent_class; 154 155 /** valid_cpu_types: NULL terminated array of a single CPU type. */ 156 const char * const *valid_cpu_types; 157 uint32_t silicon_rev; 158 uint64_t sram_size; 159 uint64_t secsram_size; 160 int spis_num; 161 int ehcis_num; 162 int wdts_num; 163 int macs_num; 164 int uarts_num; 165 int uarts_base; 166 const int *irqmap; 167 const hwaddr *memmap; 168 uint32_t num_cpus; 169 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 170 bool (*boot_from_emmc)(AspeedSoCState *s); 171 }; 172 173 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); 174 175 enum { 176 ASPEED_DEV_VBOOTROM, 177 ASPEED_DEV_SPI_BOOT, 178 ASPEED_DEV_IOMEM, 179 ASPEED_DEV_IOMEM0, 180 ASPEED_DEV_IOMEM1, 181 ASPEED_DEV_LTPI, 182 ASPEED_DEV_UART0, 183 ASPEED_DEV_UART1, 184 ASPEED_DEV_UART2, 185 ASPEED_DEV_UART3, 186 ASPEED_DEV_UART4, 187 ASPEED_DEV_UART5, 188 ASPEED_DEV_UART6, 189 ASPEED_DEV_UART7, 190 ASPEED_DEV_UART8, 191 ASPEED_DEV_UART9, 192 ASPEED_DEV_UART10, 193 ASPEED_DEV_UART11, 194 ASPEED_DEV_UART12, 195 ASPEED_DEV_UART13, 196 ASPEED_DEV_VUART, 197 ASPEED_DEV_FMC, 198 ASPEED_DEV_SPI0, 199 ASPEED_DEV_SPI1, 200 ASPEED_DEV_SPI2, 201 ASPEED_DEV_EHCI1, 202 ASPEED_DEV_EHCI2, 203 ASPEED_DEV_EHCI3, 204 ASPEED_DEV_EHCI4, 205 ASPEED_DEV_VIC, 206 ASPEED_DEV_INTC, 207 ASPEED_DEV_INTCIO, 208 ASPEED_DEV_SDMC, 209 ASPEED_DEV_SCU, 210 ASPEED_DEV_ADC, 211 ASPEED_DEV_SBC, 212 ASPEED_DEV_SECSRAM, 213 ASPEED_DEV_EMMC_BC, 214 ASPEED_DEV_VIDEO, 215 ASPEED_DEV_SRAM, 216 ASPEED_DEV_SDHCI, 217 ASPEED_DEV_GPIO, 218 ASPEED_DEV_GPIO_1_8V, 219 ASPEED_DEV_RTC, 220 ASPEED_DEV_TIMER1, 221 ASPEED_DEV_TIMER2, 222 ASPEED_DEV_TIMER3, 223 ASPEED_DEV_TIMER4, 224 ASPEED_DEV_TIMER5, 225 ASPEED_DEV_TIMER6, 226 ASPEED_DEV_TIMER7, 227 ASPEED_DEV_TIMER8, 228 ASPEED_DEV_WDT, 229 ASPEED_DEV_PWM, 230 ASPEED_DEV_LPC, 231 ASPEED_DEV_IBT, 232 ASPEED_DEV_I2C, 233 ASPEED_DEV_PECI, 234 ASPEED_DEV_ETH1, 235 ASPEED_DEV_ETH2, 236 ASPEED_DEV_ETH3, 237 ASPEED_DEV_ETH4, 238 ASPEED_DEV_MII1, 239 ASPEED_DEV_MII2, 240 ASPEED_DEV_MII3, 241 ASPEED_DEV_MII4, 242 ASPEED_DEV_SDRAM, 243 ASPEED_DEV_XDMA, 244 ASPEED_DEV_EMMC, 245 ASPEED_DEV_KCS, 246 ASPEED_DEV_HACE, 247 ASPEED_DEV_DPMCU, 248 ASPEED_DEV_DP, 249 ASPEED_DEV_I3C, 250 ASPEED_DEV_ESPI, 251 ASPEED_DEV_UDC, 252 ASPEED_DEV_SGPIOM, 253 ASPEED_DEV_JTAG0, 254 ASPEED_DEV_JTAG1, 255 ASPEED_DEV_FSI1, 256 ASPEED_DEV_FSI2, 257 ASPEED_DEV_SCUIO, 258 ASPEED_DEV_SLI, 259 ASPEED_DEV_SLIIO, 260 ASPEED_GIC_DIST, 261 ASPEED_GIC_REDIST, 262 }; 263 264 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 265 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); 266 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); 267 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 268 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 269 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 270 const char *name, hwaddr addr, 271 uint64_t size); 272 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 273 unsigned int count, int unit0); 274 275 static inline int aspeed_uart_index(int uart_dev) 276 { 277 return uart_dev - ASPEED_DEV_UART0; 278 } 279 280 static inline int aspeed_uart_first(AspeedSoCClass *sc) 281 { 282 return aspeed_uart_index(sc->uarts_base); 283 } 284 285 static inline int aspeed_uart_last(AspeedSoCClass *sc) 286 { 287 return aspeed_uart_first(sc) + sc->uarts_num - 1; 288 } 289 290 #endif /* ASPEED_SOC_H */ 291