1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/intc/aspeed_intc.h" 19 #include "hw/misc/aspeed_scu.h" 20 #include "hw/adc/aspeed_adc.h" 21 #include "hw/misc/aspeed_sdmc.h" 22 #include "hw/misc/aspeed_xdma.h" 23 #include "hw/timer/aspeed_timer.h" 24 #include "hw/rtc/aspeed_rtc.h" 25 #include "hw/i2c/aspeed_i2c.h" 26 #include "hw/misc/aspeed_i3c.h" 27 #include "hw/ssi/aspeed_smc.h" 28 #include "hw/misc/aspeed_hace.h" 29 #include "hw/misc/aspeed_sbc.h" 30 #include "hw/misc/aspeed_sli.h" 31 #include "hw/watchdog/wdt_aspeed.h" 32 #include "hw/net/ftgmac100.h" 33 #include "target/arm/cpu.h" 34 #include "hw/gpio/aspeed_gpio.h" 35 #include "hw/sd/aspeed_sdhci.h" 36 #include "hw/usb/hcd-ehci.h" 37 #include "qom/object.h" 38 #include "hw/misc/aspeed_lpc.h" 39 #include "hw/misc/unimp.h" 40 #include "hw/pci-host/aspeed_pcie.h" 41 #include "hw/misc/aspeed_peci.h" 42 #include "hw/fsi/aspeed_apb2opb.h" 43 #include "hw/char/serial-mm.h" 44 #include "hw/intc/arm_gicv3.h" 45 46 #define ASPEED_SPIS_NUM 3 47 #define ASPEED_EHCIS_NUM 4 48 #define ASPEED_WDTS_NUM 8 49 #define ASPEED_CPUS_NUM 4 50 #define ASPEED_MACS_NUM 4 51 #define ASPEED_UARTS_NUM 13 52 #define ASPEED_JTAG_NUM 2 53 #define ASPEED_PCIE_NUM 3 54 55 struct AspeedSoCState { 56 DeviceState parent; 57 58 MemoryRegion *memory; 59 MemoryRegion *dram_mr; 60 MemoryRegion dram_container; 61 MemoryRegion sram; 62 MemoryRegion spi_boot_container; 63 MemoryRegion spi_boot; 64 MemoryRegion vbootrom; 65 AddressSpace dram_as; 66 AspeedRtcState rtc; 67 AspeedTimerCtrlState timerctrl; 68 AspeedI2CState i2c; 69 AspeedI3CState i3c; 70 AspeedSCUState scu; 71 AspeedSCUState scuio; 72 AspeedHACEState hace; 73 AspeedXDMAState xdma; 74 AspeedADCState adc; 75 AspeedSMCState fmc; 76 AspeedSMCState spi[ASPEED_SPIS_NUM]; 77 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 78 AspeedSBCState sbc; 79 AspeedSLIState sli; 80 AspeedSLIState sliio; 81 MemoryRegion secsram; 82 UnimplementedDeviceState sbc_unimplemented; 83 AspeedSDMCState sdmc; 84 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 85 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 86 AspeedMiiState mii[ASPEED_MACS_NUM]; 87 AspeedGPIOState gpio; 88 AspeedGPIOState gpio_1_8v; 89 AspeedSDHCIState sdhci; 90 AspeedSDHCIState emmc; 91 AspeedLPCState lpc; 92 AspeedPCIECfgState pcie[ASPEED_PCIE_NUM]; 93 AspeedPCIEPhyState pcie_phy[ASPEED_PCIE_NUM]; 94 AspeedPECIState peci; 95 SerialMM uart[ASPEED_UARTS_NUM]; 96 Clock *sysclk; 97 UnimplementedDeviceState iomem; 98 UnimplementedDeviceState iomem0; 99 UnimplementedDeviceState iomem1; 100 UnimplementedDeviceState video; 101 UnimplementedDeviceState emmc_boot_controller; 102 UnimplementedDeviceState dpmcu; 103 UnimplementedDeviceState pwm; 104 UnimplementedDeviceState espi; 105 UnimplementedDeviceState udc; 106 UnimplementedDeviceState sgpiom; 107 UnimplementedDeviceState ltpi; 108 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; 109 AspeedAPB2OPBState fsi[2]; 110 }; 111 112 #define TYPE_ASPEED_SOC "aspeed-soc" 113 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 114 115 struct Aspeed2400SoCState { 116 AspeedSoCState parent; 117 118 ARMCPU cpu[ASPEED_CPUS_NUM]; 119 AspeedVICState vic; 120 }; 121 122 #define TYPE_ASPEED2400_SOC "aspeed2400-soc" 123 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) 124 125 struct Aspeed2600SoCState { 126 AspeedSoCState parent; 127 128 A15MPPrivState a7mpcore; 129 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */ 130 }; 131 132 #define TYPE_ASPEED2600_SOC "aspeed2600-soc" 133 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) 134 135 struct Aspeed27x0SSPSoCState { 136 AspeedSoCState parent; 137 AspeedINTCState intc[2]; 138 UnimplementedDeviceState ipc[2]; 139 UnimplementedDeviceState scuio; 140 MemoryRegion memory; 141 MemoryRegion sram_mr_alias; 142 MemoryRegion scu_mr_alias; 143 MemoryRegion sdram_remap1_alias; 144 MemoryRegion sdram_remap2_alias; 145 146 ARMv7MState armv7m; 147 }; 148 149 #define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" 150 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC) 151 152 struct Aspeed27x0TSPSoCState { 153 AspeedSoCState parent; 154 AspeedINTCState intc[2]; 155 UnimplementedDeviceState ipc[2]; 156 UnimplementedDeviceState scuio; 157 MemoryRegion memory; 158 MemoryRegion sram_mr_alias; 159 MemoryRegion scu_mr_alias; 160 MemoryRegion sdram_remap_alias; 161 162 ARMv7MState armv7m; 163 }; 164 165 #define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc" 166 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC) 167 168 struct Aspeed27x0SoCState { 169 AspeedSoCState parent; 170 171 ARMCPU cpu[ASPEED_CPUS_NUM]; 172 AspeedINTCState intc[2]; 173 GICv3State gic; 174 MemoryRegion dram_empty; 175 176 Aspeed27x0SSPSoCState ssp; 177 Aspeed27x0TSPSoCState tsp; 178 }; 179 180 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc" 181 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC) 182 183 struct Aspeed10x0SoCState { 184 AspeedSoCState parent; 185 186 ARMv7MState armv7m; 187 }; 188 189 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" 190 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) 191 192 struct AspeedSoCClass { 193 DeviceClass parent_class; 194 195 /** valid_cpu_types: NULL terminated array of a single CPU type. */ 196 const char * const *valid_cpu_types; 197 uint32_t silicon_rev; 198 uint64_t sram_size; 199 uint64_t secsram_size; 200 int spis_num; 201 int ehcis_num; 202 int wdts_num; 203 int macs_num; 204 int uarts_num; 205 int uarts_base; 206 const int *irqmap; 207 const hwaddr *memmap; 208 uint32_t num_cpus; 209 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 210 bool (*boot_from_emmc)(AspeedSoCState *s); 211 }; 212 213 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); 214 215 enum { 216 ASPEED_DEV_VBOOTROM, 217 ASPEED_DEV_SPI_BOOT, 218 ASPEED_DEV_IOMEM, 219 ASPEED_DEV_IOMEM0, 220 ASPEED_DEV_IOMEM1, 221 ASPEED_DEV_LTPI, 222 ASPEED_DEV_UART0, 223 ASPEED_DEV_UART1, 224 ASPEED_DEV_UART2, 225 ASPEED_DEV_UART3, 226 ASPEED_DEV_UART4, 227 ASPEED_DEV_UART5, 228 ASPEED_DEV_UART6, 229 ASPEED_DEV_UART7, 230 ASPEED_DEV_UART8, 231 ASPEED_DEV_UART9, 232 ASPEED_DEV_UART10, 233 ASPEED_DEV_UART11, 234 ASPEED_DEV_UART12, 235 ASPEED_DEV_UART13, 236 ASPEED_DEV_VUART, 237 ASPEED_DEV_FMC, 238 ASPEED_DEV_SPI0, 239 ASPEED_DEV_SPI1, 240 ASPEED_DEV_SPI2, 241 ASPEED_DEV_EHCI1, 242 ASPEED_DEV_EHCI2, 243 ASPEED_DEV_EHCI3, 244 ASPEED_DEV_EHCI4, 245 ASPEED_DEV_VIC, 246 ASPEED_DEV_INTC, 247 ASPEED_DEV_INTCIO, 248 ASPEED_DEV_SDMC, 249 ASPEED_DEV_SCU, 250 ASPEED_DEV_ADC, 251 ASPEED_DEV_SBC, 252 ASPEED_DEV_SECSRAM, 253 ASPEED_DEV_EMMC_BC, 254 ASPEED_DEV_VIDEO, 255 ASPEED_DEV_SRAM, 256 ASPEED_DEV_SDHCI, 257 ASPEED_DEV_GPIO, 258 ASPEED_DEV_GPIO_1_8V, 259 ASPEED_DEV_RTC, 260 ASPEED_DEV_TIMER1, 261 ASPEED_DEV_TIMER2, 262 ASPEED_DEV_TIMER3, 263 ASPEED_DEV_TIMER4, 264 ASPEED_DEV_TIMER5, 265 ASPEED_DEV_TIMER6, 266 ASPEED_DEV_TIMER7, 267 ASPEED_DEV_TIMER8, 268 ASPEED_DEV_WDT, 269 ASPEED_DEV_PWM, 270 ASPEED_DEV_LPC, 271 ASPEED_DEV_IBT, 272 ASPEED_DEV_I2C, 273 ASPEED_DEV_PCIE0, 274 ASPEED_DEV_PCIE1, 275 ASPEED_DEV_PCIE2, 276 ASPEED_DEV_PCIE_PHY0, 277 ASPEED_DEV_PCIE_PHY1, 278 ASPEED_DEV_PCIE_PHY2, 279 ASPEED_DEV_PCIE_MMIO0, 280 ASPEED_DEV_PCIE_MMIO1, 281 ASPEED_DEV_PCIE_MMIO2, 282 ASPEED_DEV_PECI, 283 ASPEED_DEV_ETH1, 284 ASPEED_DEV_ETH2, 285 ASPEED_DEV_ETH3, 286 ASPEED_DEV_ETH4, 287 ASPEED_DEV_MII1, 288 ASPEED_DEV_MII2, 289 ASPEED_DEV_MII3, 290 ASPEED_DEV_MII4, 291 ASPEED_DEV_SDRAM, 292 ASPEED_DEV_XDMA, 293 ASPEED_DEV_EMMC, 294 ASPEED_DEV_KCS, 295 ASPEED_DEV_HACE, 296 ASPEED_DEV_DPMCU, 297 ASPEED_DEV_DP, 298 ASPEED_DEV_I3C, 299 ASPEED_DEV_ESPI, 300 ASPEED_DEV_UDC, 301 ASPEED_DEV_SGPIOM, 302 ASPEED_DEV_JTAG0, 303 ASPEED_DEV_JTAG1, 304 ASPEED_DEV_FSI1, 305 ASPEED_DEV_FSI2, 306 ASPEED_DEV_SCUIO, 307 ASPEED_DEV_SLI, 308 ASPEED_DEV_SLIIO, 309 ASPEED_GIC_DIST, 310 ASPEED_GIC_REDIST, 311 ASPEED_DEV_IPC0, 312 ASPEED_DEV_IPC1, 313 }; 314 315 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 316 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); 317 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); 318 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 319 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 320 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 321 const char *name, hwaddr addr, 322 uint64_t size); 323 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 324 unsigned int count, int unit0); 325 326 static inline int aspeed_uart_index(int uart_dev) 327 { 328 return uart_dev - ASPEED_DEV_UART0; 329 } 330 331 static inline int aspeed_uart_first(AspeedSoCClass *sc) 332 { 333 return aspeed_uart_index(sc->uarts_base); 334 } 335 336 static inline int aspeed_uart_last(AspeedSoCClass *sc) 337 { 338 return aspeed_uart_first(sc) + sc->uarts_num - 1; 339 } 340 341 #endif /* ASPEED_SOC_H */ 342