1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/intc/aspeed_vic.h" 17 #include "hw/misc/aspeed_scu.h" 18 #include "hw/adc/aspeed_adc.h" 19 #include "hw/misc/aspeed_sdmc.h" 20 #include "hw/misc/aspeed_xdma.h" 21 #include "hw/timer/aspeed_timer.h" 22 #include "hw/rtc/aspeed_rtc.h" 23 #include "hw/i2c/aspeed_i2c.h" 24 #include "hw/misc/aspeed_i3c.h" 25 #include "hw/ssi/aspeed_smc.h" 26 #include "hw/misc/aspeed_hace.h" 27 #include "hw/watchdog/wdt_aspeed.h" 28 #include "hw/net/ftgmac100.h" 29 #include "target/arm/cpu.h" 30 #include "hw/gpio/aspeed_gpio.h" 31 #include "hw/sd/aspeed_sdhci.h" 32 #include "hw/usb/hcd-ehci.h" 33 #include "qom/object.h" 34 #include "hw/misc/aspeed_lpc.h" 35 36 #define ASPEED_SPIS_NUM 2 37 #define ASPEED_EHCIS_NUM 2 38 #define ASPEED_WDTS_NUM 4 39 #define ASPEED_CPUS_NUM 2 40 #define ASPEED_MACS_NUM 4 41 42 struct AspeedSoCState { 43 /*< private >*/ 44 DeviceState parent; 45 46 /*< public >*/ 47 ARMCPU cpu[ASPEED_CPUS_NUM]; 48 A15MPPrivState a7mpcore; 49 MemoryRegion *dram_mr; 50 MemoryRegion sram; 51 AspeedVICState vic; 52 AspeedRtcState rtc; 53 AspeedTimerCtrlState timerctrl; 54 AspeedI2CState i2c; 55 AspeedI3CState i3c; 56 AspeedSCUState scu; 57 AspeedHACEState hace; 58 AspeedXDMAState xdma; 59 AspeedADCState adc; 60 AspeedSMCState fmc; 61 AspeedSMCState spi[ASPEED_SPIS_NUM]; 62 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 63 AspeedSDMCState sdmc; 64 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 65 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 66 AspeedMiiState mii[ASPEED_MACS_NUM]; 67 AspeedGPIOState gpio; 68 AspeedGPIOState gpio_1_8v; 69 AspeedSDHCIState sdhci; 70 AspeedSDHCIState emmc; 71 AspeedLPCState lpc; 72 uint32_t uart_default; 73 }; 74 75 #define TYPE_ASPEED_SOC "aspeed-soc" 76 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 77 78 struct AspeedSoCClass { 79 DeviceClass parent_class; 80 81 const char *name; 82 const char *cpu_type; 83 uint32_t silicon_rev; 84 uint64_t sram_size; 85 int spis_num; 86 int ehcis_num; 87 int wdts_num; 88 int macs_num; 89 const int *irqmap; 90 const hwaddr *memmap; 91 uint32_t num_cpus; 92 }; 93 94 95 enum { 96 ASPEED_DEV_IOMEM, 97 ASPEED_DEV_UART1, 98 ASPEED_DEV_UART2, 99 ASPEED_DEV_UART3, 100 ASPEED_DEV_UART4, 101 ASPEED_DEV_UART5, 102 ASPEED_DEV_VUART, 103 ASPEED_DEV_FMC, 104 ASPEED_DEV_SPI1, 105 ASPEED_DEV_SPI2, 106 ASPEED_DEV_EHCI1, 107 ASPEED_DEV_EHCI2, 108 ASPEED_DEV_VIC, 109 ASPEED_DEV_SDMC, 110 ASPEED_DEV_SCU, 111 ASPEED_DEV_ADC, 112 ASPEED_DEV_VIDEO, 113 ASPEED_DEV_SRAM, 114 ASPEED_DEV_SDHCI, 115 ASPEED_DEV_GPIO, 116 ASPEED_DEV_GPIO_1_8V, 117 ASPEED_DEV_RTC, 118 ASPEED_DEV_TIMER1, 119 ASPEED_DEV_TIMER2, 120 ASPEED_DEV_TIMER3, 121 ASPEED_DEV_TIMER4, 122 ASPEED_DEV_TIMER5, 123 ASPEED_DEV_TIMER6, 124 ASPEED_DEV_TIMER7, 125 ASPEED_DEV_TIMER8, 126 ASPEED_DEV_WDT, 127 ASPEED_DEV_PWM, 128 ASPEED_DEV_LPC, 129 ASPEED_DEV_IBT, 130 ASPEED_DEV_I2C, 131 ASPEED_DEV_ETH1, 132 ASPEED_DEV_ETH2, 133 ASPEED_DEV_ETH3, 134 ASPEED_DEV_ETH4, 135 ASPEED_DEV_MII1, 136 ASPEED_DEV_MII2, 137 ASPEED_DEV_MII3, 138 ASPEED_DEV_MII4, 139 ASPEED_DEV_SDRAM, 140 ASPEED_DEV_XDMA, 141 ASPEED_DEV_EMMC, 142 ASPEED_DEV_KCS, 143 ASPEED_DEV_HACE, 144 ASPEED_DEV_DPMCU, 145 ASPEED_DEV_DP, 146 ASPEED_DEV_I3C, 147 }; 148 149 #endif /* ASPEED_SOC_H */ 150