1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/intc/aspeed_vic.h" 17 #include "hw/misc/aspeed_scu.h" 18 #include "hw/misc/aspeed_sdmc.h" 19 #include "hw/misc/aspeed_xdma.h" 20 #include "hw/timer/aspeed_timer.h" 21 #include "hw/rtc/aspeed_rtc.h" 22 #include "hw/i2c/aspeed_i2c.h" 23 #include "hw/ssi/aspeed_smc.h" 24 #include "hw/watchdog/wdt_aspeed.h" 25 #include "hw/net/ftgmac100.h" 26 #include "target/arm/cpu.h" 27 #include "hw/gpio/aspeed_gpio.h" 28 #include "hw/sd/aspeed_sdhci.h" 29 #include "hw/usb/hcd-ehci.h" 30 31 #define ASPEED_SPIS_NUM 2 32 #define ASPEED_EHCIS_NUM 2 33 #define ASPEED_WDTS_NUM 4 34 #define ASPEED_CPUS_NUM 2 35 #define ASPEED_MACS_NUM 4 36 37 typedef struct AspeedSoCState { 38 /*< private >*/ 39 DeviceState parent; 40 41 /*< public >*/ 42 ARMCPU cpu[ASPEED_CPUS_NUM]; 43 A15MPPrivState a7mpcore; 44 MemoryRegion *dram_mr; 45 MemoryRegion sram; 46 AspeedVICState vic; 47 AspeedRtcState rtc; 48 AspeedTimerCtrlState timerctrl; 49 AspeedI2CState i2c; 50 AspeedSCUState scu; 51 AspeedXDMAState xdma; 52 AspeedSMCState fmc; 53 AspeedSMCState spi[ASPEED_SPIS_NUM]; 54 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 55 AspeedSDMCState sdmc; 56 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 57 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 58 AspeedMiiState mii[ASPEED_MACS_NUM]; 59 AspeedGPIOState gpio; 60 AspeedGPIOState gpio_1_8v; 61 AspeedSDHCIState sdhci; 62 AspeedSDHCIState emmc; 63 } AspeedSoCState; 64 65 #define TYPE_ASPEED_SOC "aspeed-soc" 66 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC) 67 68 typedef struct AspeedSoCClass { 69 DeviceClass parent_class; 70 71 const char *name; 72 const char *cpu_type; 73 uint32_t silicon_rev; 74 uint64_t sram_size; 75 int spis_num; 76 int ehcis_num; 77 int wdts_num; 78 int macs_num; 79 const int *irqmap; 80 const hwaddr *memmap; 81 uint32_t num_cpus; 82 } AspeedSoCClass; 83 84 #define ASPEED_SOC_CLASS(klass) \ 85 OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC) 86 #define ASPEED_SOC_GET_CLASS(obj) \ 87 OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC) 88 89 enum { 90 ASPEED_DEV_IOMEM, 91 ASPEED_DEV_UART1, 92 ASPEED_DEV_UART2, 93 ASPEED_DEV_UART3, 94 ASPEED_DEV_UART4, 95 ASPEED_DEV_UART5, 96 ASPEED_DEV_VUART, 97 ASPEED_DEV_FMC, 98 ASPEED_DEV_SPI1, 99 ASPEED_DEV_SPI2, 100 ASPEED_DEV_EHCI1, 101 ASPEED_DEV_EHCI2, 102 ASPEED_DEV_VIC, 103 ASPEED_DEV_SDMC, 104 ASPEED_DEV_SCU, 105 ASPEED_DEV_ADC, 106 ASPEED_DEV_VIDEO, 107 ASPEED_DEV_SRAM, 108 ASPEED_DEV_SDHCI, 109 ASPEED_DEV_GPIO, 110 ASPEED_DEV_GPIO_1_8V, 111 ASPEED_DEV_RTC, 112 ASPEED_DEV_TIMER1, 113 ASPEED_DEV_TIMER2, 114 ASPEED_DEV_TIMER3, 115 ASPEED_DEV_TIMER4, 116 ASPEED_DEV_TIMER5, 117 ASPEED_DEV_TIMER6, 118 ASPEED_DEV_TIMER7, 119 ASPEED_DEV_TIMER8, 120 ASPEED_DEV_WDT, 121 ASPEED_DEV_PWM, 122 ASPEED_DEV_LPC, 123 ASPEED_DEV_IBT, 124 ASPEED_DEV_I2C, 125 ASPEED_DEV_ETH1, 126 ASPEED_DEV_ETH2, 127 ASPEED_DEV_ETH3, 128 ASPEED_DEV_ETH4, 129 ASPEED_DEV_MII1, 130 ASPEED_DEV_MII2, 131 ASPEED_DEV_MII3, 132 ASPEED_DEV_MII4, 133 ASPEED_DEV_SDRAM, 134 ASPEED_DEV_XDMA, 135 ASPEED_DEV_EMMC, 136 }; 137 138 #endif /* ASPEED_SOC_H */ 139