1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/misc/aspeed_scu.h" 19 #include "hw/adc/aspeed_adc.h" 20 #include "hw/misc/aspeed_sdmc.h" 21 #include "hw/misc/aspeed_xdma.h" 22 #include "hw/timer/aspeed_timer.h" 23 #include "hw/rtc/aspeed_rtc.h" 24 #include "hw/i2c/aspeed_i2c.h" 25 #include "hw/misc/aspeed_i3c.h" 26 #include "hw/ssi/aspeed_smc.h" 27 #include "hw/misc/aspeed_hace.h" 28 #include "hw/misc/aspeed_sbc.h" 29 #include "hw/watchdog/wdt_aspeed.h" 30 #include "hw/net/ftgmac100.h" 31 #include "target/arm/cpu.h" 32 #include "hw/gpio/aspeed_gpio.h" 33 #include "hw/sd/aspeed_sdhci.h" 34 #include "hw/usb/hcd-ehci.h" 35 #include "qom/object.h" 36 #include "hw/misc/aspeed_lpc.h" 37 38 #define ASPEED_SPIS_NUM 2 39 #define ASPEED_EHCIS_NUM 2 40 #define ASPEED_WDTS_NUM 4 41 #define ASPEED_CPUS_NUM 2 42 #define ASPEED_MACS_NUM 4 43 44 struct AspeedSoCState { 45 /*< private >*/ 46 DeviceState parent; 47 48 /*< public >*/ 49 ARMCPU cpu[ASPEED_CPUS_NUM]; 50 A15MPPrivState a7mpcore; 51 ARMv7MState armv7m; 52 MemoryRegion *dram_mr; 53 MemoryRegion dram_container; 54 MemoryRegion sram; 55 AspeedVICState vic; 56 AspeedRtcState rtc; 57 AspeedTimerCtrlState timerctrl; 58 AspeedI2CState i2c; 59 AspeedI3CState i3c; 60 AspeedSCUState scu; 61 AspeedHACEState hace; 62 AspeedXDMAState xdma; 63 AspeedADCState adc; 64 AspeedSMCState fmc; 65 AspeedSMCState spi[ASPEED_SPIS_NUM]; 66 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 67 AspeedSBCState sbc; 68 AspeedSDMCState sdmc; 69 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 70 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 71 AspeedMiiState mii[ASPEED_MACS_NUM]; 72 AspeedGPIOState gpio; 73 AspeedGPIOState gpio_1_8v; 74 AspeedSDHCIState sdhci; 75 AspeedSDHCIState emmc; 76 AspeedLPCState lpc; 77 uint32_t uart_default; 78 Clock *sysclk; 79 }; 80 81 #define TYPE_ASPEED_SOC "aspeed-soc" 82 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 83 84 struct AspeedSoCClass { 85 DeviceClass parent_class; 86 87 const char *name; 88 const char *cpu_type; 89 uint32_t silicon_rev; 90 uint64_t sram_size; 91 int spis_num; 92 int ehcis_num; 93 int wdts_num; 94 int macs_num; 95 int uarts_num; 96 const int *irqmap; 97 const hwaddr *memmap; 98 uint32_t num_cpus; 99 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 100 }; 101 102 103 enum { 104 ASPEED_DEV_IOMEM, 105 ASPEED_DEV_UART1, 106 ASPEED_DEV_UART2, 107 ASPEED_DEV_UART3, 108 ASPEED_DEV_UART4, 109 ASPEED_DEV_UART5, 110 ASPEED_DEV_UART6, 111 ASPEED_DEV_UART7, 112 ASPEED_DEV_UART8, 113 ASPEED_DEV_UART9, 114 ASPEED_DEV_UART10, 115 ASPEED_DEV_UART11, 116 ASPEED_DEV_UART12, 117 ASPEED_DEV_UART13, 118 ASPEED_DEV_VUART, 119 ASPEED_DEV_FMC, 120 ASPEED_DEV_SPI1, 121 ASPEED_DEV_SPI2, 122 ASPEED_DEV_EHCI1, 123 ASPEED_DEV_EHCI2, 124 ASPEED_DEV_VIC, 125 ASPEED_DEV_SDMC, 126 ASPEED_DEV_SCU, 127 ASPEED_DEV_ADC, 128 ASPEED_DEV_SBC, 129 ASPEED_DEV_EMMC_BC, 130 ASPEED_DEV_VIDEO, 131 ASPEED_DEV_SRAM, 132 ASPEED_DEV_SDHCI, 133 ASPEED_DEV_GPIO, 134 ASPEED_DEV_GPIO_1_8V, 135 ASPEED_DEV_RTC, 136 ASPEED_DEV_TIMER1, 137 ASPEED_DEV_TIMER2, 138 ASPEED_DEV_TIMER3, 139 ASPEED_DEV_TIMER4, 140 ASPEED_DEV_TIMER5, 141 ASPEED_DEV_TIMER6, 142 ASPEED_DEV_TIMER7, 143 ASPEED_DEV_TIMER8, 144 ASPEED_DEV_WDT, 145 ASPEED_DEV_PWM, 146 ASPEED_DEV_LPC, 147 ASPEED_DEV_IBT, 148 ASPEED_DEV_I2C, 149 ASPEED_DEV_ETH1, 150 ASPEED_DEV_ETH2, 151 ASPEED_DEV_ETH3, 152 ASPEED_DEV_ETH4, 153 ASPEED_DEV_MII1, 154 ASPEED_DEV_MII2, 155 ASPEED_DEV_MII3, 156 ASPEED_DEV_MII4, 157 ASPEED_DEV_SDRAM, 158 ASPEED_DEV_XDMA, 159 ASPEED_DEV_EMMC, 160 ASPEED_DEV_KCS, 161 ASPEED_DEV_HACE, 162 ASPEED_DEV_DPMCU, 163 ASPEED_DEV_DP, 164 ASPEED_DEV_I3C, 165 }; 166 167 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 168 void aspeed_soc_uart_init(AspeedSoCState *s); 169 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 170 171 #endif /* ASPEED_SOC_H */ 172