1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/intc/aspeed_vic.h" 17 #include "hw/misc/aspeed_scu.h" 18 #include "hw/adc/aspeed_adc.h" 19 #include "hw/misc/aspeed_sdmc.h" 20 #include "hw/misc/aspeed_xdma.h" 21 #include "hw/timer/aspeed_timer.h" 22 #include "hw/rtc/aspeed_rtc.h" 23 #include "hw/i2c/aspeed_i2c.h" 24 #include "hw/misc/aspeed_i3c.h" 25 #include "hw/ssi/aspeed_smc.h" 26 #include "hw/misc/aspeed_hace.h" 27 #include "hw/misc/aspeed_sbc.h" 28 #include "hw/watchdog/wdt_aspeed.h" 29 #include "hw/net/ftgmac100.h" 30 #include "target/arm/cpu.h" 31 #include "hw/gpio/aspeed_gpio.h" 32 #include "hw/sd/aspeed_sdhci.h" 33 #include "hw/usb/hcd-ehci.h" 34 #include "qom/object.h" 35 #include "hw/misc/aspeed_lpc.h" 36 37 #define ASPEED_SPIS_NUM 2 38 #define ASPEED_EHCIS_NUM 2 39 #define ASPEED_WDTS_NUM 4 40 #define ASPEED_CPUS_NUM 2 41 #define ASPEED_MACS_NUM 4 42 43 struct AspeedSoCState { 44 /*< private >*/ 45 DeviceState parent; 46 47 /*< public >*/ 48 ARMCPU cpu[ASPEED_CPUS_NUM]; 49 A15MPPrivState a7mpcore; 50 MemoryRegion *dram_mr; 51 MemoryRegion sram; 52 AspeedVICState vic; 53 AspeedRtcState rtc; 54 AspeedTimerCtrlState timerctrl; 55 AspeedI2CState i2c; 56 AspeedI3CState i3c; 57 AspeedSCUState scu; 58 AspeedHACEState hace; 59 AspeedXDMAState xdma; 60 AspeedADCState adc; 61 AspeedSMCState fmc; 62 AspeedSMCState spi[ASPEED_SPIS_NUM]; 63 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 64 AspeedSBCState sbc; 65 AspeedSDMCState sdmc; 66 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 67 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 68 AspeedMiiState mii[ASPEED_MACS_NUM]; 69 AspeedGPIOState gpio; 70 AspeedGPIOState gpio_1_8v; 71 AspeedSDHCIState sdhci; 72 AspeedSDHCIState emmc; 73 AspeedLPCState lpc; 74 uint32_t uart_default; 75 }; 76 77 #define TYPE_ASPEED_SOC "aspeed-soc" 78 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 79 80 struct AspeedSoCClass { 81 DeviceClass parent_class; 82 83 const char *name; 84 const char *cpu_type; 85 uint32_t silicon_rev; 86 uint64_t sram_size; 87 int spis_num; 88 int ehcis_num; 89 int wdts_num; 90 int macs_num; 91 const int *irqmap; 92 const hwaddr *memmap; 93 uint32_t num_cpus; 94 }; 95 96 97 enum { 98 ASPEED_DEV_IOMEM, 99 ASPEED_DEV_UART1, 100 ASPEED_DEV_UART2, 101 ASPEED_DEV_UART3, 102 ASPEED_DEV_UART4, 103 ASPEED_DEV_UART5, 104 ASPEED_DEV_VUART, 105 ASPEED_DEV_FMC, 106 ASPEED_DEV_SPI1, 107 ASPEED_DEV_SPI2, 108 ASPEED_DEV_EHCI1, 109 ASPEED_DEV_EHCI2, 110 ASPEED_DEV_VIC, 111 ASPEED_DEV_SDMC, 112 ASPEED_DEV_SCU, 113 ASPEED_DEV_ADC, 114 ASPEED_DEV_SBC, 115 ASPEED_DEV_VIDEO, 116 ASPEED_DEV_SRAM, 117 ASPEED_DEV_SDHCI, 118 ASPEED_DEV_GPIO, 119 ASPEED_DEV_GPIO_1_8V, 120 ASPEED_DEV_RTC, 121 ASPEED_DEV_TIMER1, 122 ASPEED_DEV_TIMER2, 123 ASPEED_DEV_TIMER3, 124 ASPEED_DEV_TIMER4, 125 ASPEED_DEV_TIMER5, 126 ASPEED_DEV_TIMER6, 127 ASPEED_DEV_TIMER7, 128 ASPEED_DEV_TIMER8, 129 ASPEED_DEV_WDT, 130 ASPEED_DEV_PWM, 131 ASPEED_DEV_LPC, 132 ASPEED_DEV_IBT, 133 ASPEED_DEV_I2C, 134 ASPEED_DEV_ETH1, 135 ASPEED_DEV_ETH2, 136 ASPEED_DEV_ETH3, 137 ASPEED_DEV_ETH4, 138 ASPEED_DEV_MII1, 139 ASPEED_DEV_MII2, 140 ASPEED_DEV_MII3, 141 ASPEED_DEV_MII4, 142 ASPEED_DEV_SDRAM, 143 ASPEED_DEV_XDMA, 144 ASPEED_DEV_EMMC, 145 ASPEED_DEV_KCS, 146 ASPEED_DEV_HACE, 147 ASPEED_DEV_DPMCU, 148 ASPEED_DEV_DP, 149 ASPEED_DEV_I3C, 150 }; 151 152 #endif /* ASPEED_SOC_H */ 153