1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/intc/aspeed_vic.h" 16 #include "hw/misc/aspeed_scu.h" 17 #include "hw/misc/aspeed_sdmc.h" 18 #include "hw/misc/aspeed_xdma.h" 19 #include "hw/timer/aspeed_timer.h" 20 #include "hw/timer/aspeed_rtc.h" 21 #include "hw/i2c/aspeed_i2c.h" 22 #include "hw/ssi/aspeed_smc.h" 23 #include "hw/watchdog/wdt_aspeed.h" 24 #include "hw/net/ftgmac100.h" 25 26 #define ASPEED_SPIS_NUM 2 27 #define ASPEED_WDTS_NUM 3 28 #define ASPEED_CPUS_NUM 2 29 #define ASPEED_MACS_NUM 2 30 31 typedef struct AspeedSoCState { 32 /*< private >*/ 33 DeviceState parent; 34 35 /*< public >*/ 36 ARMCPU cpu[ASPEED_CPUS_NUM]; 37 uint32_t num_cpus; 38 MemoryRegion sram; 39 AspeedVICState vic; 40 AspeedRtcState rtc; 41 AspeedTimerCtrlState timerctrl; 42 AspeedI2CState i2c; 43 AspeedSCUState scu; 44 AspeedXDMAState xdma; 45 AspeedSMCState fmc; 46 AspeedSMCState spi[ASPEED_SPIS_NUM]; 47 AspeedSDMCState sdmc; 48 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 49 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 50 } AspeedSoCState; 51 52 #define TYPE_ASPEED_SOC "aspeed-soc" 53 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC) 54 55 typedef struct AspeedSoCInfo { 56 const char *name; 57 const char *cpu_type; 58 uint32_t silicon_rev; 59 uint64_t sram_size; 60 int spis_num; 61 const char *fmc_typename; 62 const char **spi_typename; 63 int wdts_num; 64 const int *irqmap; 65 const hwaddr *memmap; 66 uint32_t num_cpus; 67 } AspeedSoCInfo; 68 69 typedef struct AspeedSoCClass { 70 DeviceClass parent_class; 71 AspeedSoCInfo *info; 72 } AspeedSoCClass; 73 74 #define ASPEED_SOC_CLASS(klass) \ 75 OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC) 76 #define ASPEED_SOC_GET_CLASS(obj) \ 77 OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC) 78 79 enum { 80 ASPEED_IOMEM, 81 ASPEED_UART1, 82 ASPEED_UART2, 83 ASPEED_UART3, 84 ASPEED_UART4, 85 ASPEED_UART5, 86 ASPEED_VUART, 87 ASPEED_FMC, 88 ASPEED_SPI1, 89 ASPEED_SPI2, 90 ASPEED_VIC, 91 ASPEED_SDMC, 92 ASPEED_SCU, 93 ASPEED_ADC, 94 ASPEED_SRAM, 95 ASPEED_GPIO, 96 ASPEED_RTC, 97 ASPEED_TIMER1, 98 ASPEED_TIMER2, 99 ASPEED_TIMER3, 100 ASPEED_TIMER4, 101 ASPEED_TIMER5, 102 ASPEED_TIMER6, 103 ASPEED_TIMER7, 104 ASPEED_TIMER8, 105 ASPEED_WDT, 106 ASPEED_PWM, 107 ASPEED_LPC, 108 ASPEED_IBT, 109 ASPEED_I2C, 110 ASPEED_ETH1, 111 ASPEED_ETH2, 112 ASPEED_SDRAM, 113 ASPEED_XDMA, 114 }; 115 116 #endif /* ASPEED_SOC_H */ 117