1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/intc/aspeed_intc.h" 19 #include "hw/misc/aspeed_scu.h" 20 #include "hw/adc/aspeed_adc.h" 21 #include "hw/misc/aspeed_sdmc.h" 22 #include "hw/misc/aspeed_xdma.h" 23 #include "hw/timer/aspeed_timer.h" 24 #include "hw/rtc/aspeed_rtc.h" 25 #include "hw/i2c/aspeed_i2c.h" 26 #include "hw/misc/aspeed_i3c.h" 27 #include "hw/ssi/aspeed_smc.h" 28 #include "hw/misc/aspeed_hace.h" 29 #include "hw/misc/aspeed_sbc.h" 30 #include "hw/misc/aspeed_sli.h" 31 #include "hw/watchdog/wdt_aspeed.h" 32 #include "hw/net/ftgmac100.h" 33 #include "target/arm/cpu.h" 34 #include "hw/gpio/aspeed_gpio.h" 35 #include "hw/sd/aspeed_sdhci.h" 36 #include "hw/usb/hcd-ehci.h" 37 #include "hw/usb/hcd-uhci-sysbus.h" 38 #include "qom/object.h" 39 #include "hw/misc/aspeed_lpc.h" 40 #include "hw/misc/unimp.h" 41 #include "hw/misc/aspeed_peci.h" 42 #include "hw/fsi/aspeed_apb2opb.h" 43 #include "hw/char/serial-mm.h" 44 #include "hw/intc/arm_gicv3.h" 45 46 #define ASPEED_SPIS_NUM 2 47 #define ASPEED_EHCIS_NUM 2 48 #define ASPEED_WDTS_NUM 8 49 #define ASPEED_CPUS_NUM 4 50 #define ASPEED_MACS_NUM 4 51 #define ASPEED_UARTS_NUM 13 52 #define ASPEED_JTAG_NUM 2 53 54 struct AspeedSoCState { 55 DeviceState parent; 56 57 MemoryRegion *memory; 58 MemoryRegion *dram_mr; 59 MemoryRegion dram_container; 60 MemoryRegion sram; 61 MemoryRegion spi_boot_container; 62 MemoryRegion spi_boot; 63 AddressSpace dram_as; 64 AspeedRtcState rtc; 65 AspeedTimerCtrlState timerctrl; 66 AspeedI2CState i2c; 67 AspeedI3CState i3c; 68 AspeedSCUState scu; 69 AspeedSCUState scuio; 70 AspeedHACEState hace; 71 AspeedXDMAState xdma; 72 AspeedADCState adc; 73 AspeedSMCState fmc; 74 AspeedSMCState spi[ASPEED_SPIS_NUM]; 75 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 76 ASPEEDUHCIState uhci; 77 AspeedSBCState sbc; 78 AspeedSLIState sli; 79 AspeedSLIState sliio; 80 MemoryRegion secsram; 81 UnimplementedDeviceState sbc_unimplemented; 82 AspeedSDMCState sdmc; 83 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 84 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 85 AspeedMiiState mii[ASPEED_MACS_NUM]; 86 AspeedGPIOState gpio; 87 AspeedGPIOState gpio_1_8v; 88 AspeedSDHCIState sdhci; 89 AspeedSDHCIState emmc; 90 AspeedLPCState lpc; 91 AspeedPECIState peci; 92 SerialMM uart[ASPEED_UARTS_NUM]; 93 Clock *sysclk; 94 UnimplementedDeviceState iomem; 95 UnimplementedDeviceState video; 96 UnimplementedDeviceState emmc_boot_controller; 97 UnimplementedDeviceState dpmcu; 98 UnimplementedDeviceState pwm; 99 UnimplementedDeviceState espi; 100 UnimplementedDeviceState udc; 101 UnimplementedDeviceState sgpiom; 102 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; 103 AspeedAPB2OPBState fsi[2]; 104 }; 105 106 #define TYPE_ASPEED_SOC "aspeed-soc" 107 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 108 109 struct Aspeed2400SoCState { 110 AspeedSoCState parent; 111 112 ARMCPU cpu[ASPEED_CPUS_NUM]; 113 AspeedVICState vic; 114 }; 115 116 #define TYPE_ASPEED2400_SOC "aspeed2400-soc" 117 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) 118 119 struct Aspeed2600SoCState { 120 AspeedSoCState parent; 121 122 A15MPPrivState a7mpcore; 123 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */ 124 }; 125 126 #define TYPE_ASPEED2600_SOC "aspeed2600-soc" 127 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) 128 129 struct Aspeed27x0SoCState { 130 AspeedSoCState parent; 131 132 ARMCPU cpu[ASPEED_CPUS_NUM]; 133 AspeedINTCState intc; 134 GICv3State gic; 135 MemoryRegion dram_empty; 136 }; 137 138 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc" 139 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC) 140 141 struct Aspeed10x0SoCState { 142 AspeedSoCState parent; 143 144 ARMv7MState armv7m; 145 }; 146 147 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" 148 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) 149 150 struct AspeedSoCClass { 151 DeviceClass parent_class; 152 153 const char *name; 154 /** valid_cpu_types: NULL terminated array of a single CPU type. */ 155 const char * const *valid_cpu_types; 156 uint32_t silicon_rev; 157 uint64_t sram_size; 158 uint64_t secsram_size; 159 int spis_num; 160 int ehcis_num; 161 int wdts_num; 162 int macs_num; 163 int uarts_num; 164 int uarts_base; 165 const int *irqmap; 166 const hwaddr *memmap; 167 uint32_t num_cpus; 168 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 169 bool (*boot_from_emmc)(AspeedSoCState *s); 170 }; 171 172 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); 173 174 enum { 175 ASPEED_DEV_SPI_BOOT, 176 ASPEED_DEV_IOMEM, 177 ASPEED_DEV_UART0, 178 ASPEED_DEV_UART1, 179 ASPEED_DEV_UART2, 180 ASPEED_DEV_UART3, 181 ASPEED_DEV_UART4, 182 ASPEED_DEV_UART5, 183 ASPEED_DEV_UART6, 184 ASPEED_DEV_UART7, 185 ASPEED_DEV_UART8, 186 ASPEED_DEV_UART9, 187 ASPEED_DEV_UART10, 188 ASPEED_DEV_UART11, 189 ASPEED_DEV_UART12, 190 ASPEED_DEV_UART13, 191 ASPEED_DEV_VUART, 192 ASPEED_DEV_FMC, 193 ASPEED_DEV_SPI0, 194 ASPEED_DEV_SPI1, 195 ASPEED_DEV_SPI2, 196 ASPEED_DEV_EHCI1, 197 ASPEED_DEV_EHCI2, 198 ASPEED_DEV_UHCI, 199 ASPEED_DEV_VIC, 200 ASPEED_DEV_INTC, 201 ASPEED_DEV_SDMC, 202 ASPEED_DEV_SCU, 203 ASPEED_DEV_ADC, 204 ASPEED_DEV_SBC, 205 ASPEED_DEV_SECSRAM, 206 ASPEED_DEV_EMMC_BC, 207 ASPEED_DEV_VIDEO, 208 ASPEED_DEV_SRAM, 209 ASPEED_DEV_SDHCI, 210 ASPEED_DEV_GPIO, 211 ASPEED_DEV_GPIO_1_8V, 212 ASPEED_DEV_RTC, 213 ASPEED_DEV_TIMER1, 214 ASPEED_DEV_TIMER2, 215 ASPEED_DEV_TIMER3, 216 ASPEED_DEV_TIMER4, 217 ASPEED_DEV_TIMER5, 218 ASPEED_DEV_TIMER6, 219 ASPEED_DEV_TIMER7, 220 ASPEED_DEV_TIMER8, 221 ASPEED_DEV_WDT, 222 ASPEED_DEV_PWM, 223 ASPEED_DEV_LPC, 224 ASPEED_DEV_IBT, 225 ASPEED_DEV_I2C, 226 ASPEED_DEV_PECI, 227 ASPEED_DEV_ETH1, 228 ASPEED_DEV_ETH2, 229 ASPEED_DEV_ETH3, 230 ASPEED_DEV_ETH4, 231 ASPEED_DEV_MII1, 232 ASPEED_DEV_MII2, 233 ASPEED_DEV_MII3, 234 ASPEED_DEV_MII4, 235 ASPEED_DEV_SDRAM, 236 ASPEED_DEV_XDMA, 237 ASPEED_DEV_EMMC, 238 ASPEED_DEV_KCS, 239 ASPEED_DEV_HACE, 240 ASPEED_DEV_DPMCU, 241 ASPEED_DEV_DP, 242 ASPEED_DEV_I3C, 243 ASPEED_DEV_ESPI, 244 ASPEED_DEV_UDC, 245 ASPEED_DEV_SGPIOM, 246 ASPEED_DEV_JTAG0, 247 ASPEED_DEV_JTAG1, 248 ASPEED_DEV_FSI1, 249 ASPEED_DEV_FSI2, 250 ASPEED_DEV_SCUIO, 251 ASPEED_DEV_SLI, 252 ASPEED_DEV_SLIIO, 253 ASPEED_GIC_DIST, 254 ASPEED_GIC_REDIST, 255 }; 256 257 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 258 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); 259 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); 260 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 261 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 262 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 263 const char *name, hwaddr addr, 264 uint64_t size); 265 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 266 unsigned int count, int unit0); 267 268 static inline int aspeed_uart_index(int uart_dev) 269 { 270 return uart_dev - ASPEED_DEV_UART0; 271 } 272 273 static inline int aspeed_uart_first(AspeedSoCClass *sc) 274 { 275 return aspeed_uart_index(sc->uarts_base); 276 } 277 278 static inline int aspeed_uart_last(AspeedSoCClass *sc) 279 { 280 return aspeed_uart_first(sc) + sc->uarts_num - 1; 281 } 282 283 #endif /* ASPEED_SOC_H */ 284