1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/arm/arm.h" 16 #include "hw/intc/aspeed_vic.h" 17 #include "hw/misc/aspeed_scu.h" 18 #include "hw/misc/aspeed_sdmc.h" 19 #include "hw/timer/aspeed_timer.h" 20 #include "hw/i2c/aspeed_i2c.h" 21 #include "hw/ssi/aspeed_smc.h" 22 #include "hw/watchdog/wdt_aspeed.h" 23 #include "hw/net/ftgmac100.h" 24 25 #define ASPEED_SPIS_NUM 2 26 #define ASPEED_WDTS_NUM 3 27 28 typedef struct AspeedSoCState { 29 /*< private >*/ 30 DeviceState parent; 31 32 /*< public >*/ 33 ARMCPU cpu; 34 MemoryRegion iomem; 35 MemoryRegion sram; 36 AspeedVICState vic; 37 AspeedTimerCtrlState timerctrl; 38 AspeedI2CState i2c; 39 AspeedSCUState scu; 40 AspeedSMCState fmc; 41 AspeedSMCState spi[ASPEED_SPIS_NUM]; 42 AspeedSDMCState sdmc; 43 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 44 FTGMAC100State ftgmac100; 45 } AspeedSoCState; 46 47 #define TYPE_ASPEED_SOC "aspeed-soc" 48 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC) 49 50 typedef struct AspeedSoCInfo { 51 const char *name; 52 const char *cpu_type; 53 uint32_t silicon_rev; 54 hwaddr sdram_base; 55 uint64_t sram_size; 56 int spis_num; 57 const hwaddr *spi_bases; 58 const char *fmc_typename; 59 const char **spi_typename; 60 int wdts_num; 61 } AspeedSoCInfo; 62 63 typedef struct AspeedSoCClass { 64 DeviceClass parent_class; 65 AspeedSoCInfo *info; 66 } AspeedSoCClass; 67 68 #define ASPEED_SOC_CLASS(klass) \ 69 OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC) 70 #define ASPEED_SOC_GET_CLASS(obj) \ 71 OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC) 72 73 #endif /* ASPEED_SOC_H */ 74