1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/intc/aspeed_vic.h" 16 #include "hw/misc/aspeed_scu.h" 17 #include "hw/misc/aspeed_sdmc.h" 18 #include "hw/timer/aspeed_timer.h" 19 #include "hw/i2c/aspeed_i2c.h" 20 #include "hw/ssi/aspeed_smc.h" 21 #include "hw/watchdog/wdt_aspeed.h" 22 #include "hw/net/ftgmac100.h" 23 24 #define ASPEED_SPIS_NUM 2 25 #define ASPEED_WDTS_NUM 3 26 27 typedef struct AspeedSoCState { 28 /*< private >*/ 29 DeviceState parent; 30 31 /*< public >*/ 32 ARMCPU cpu; 33 MemoryRegion sram; 34 AspeedVICState vic; 35 AspeedTimerCtrlState timerctrl; 36 AspeedI2CState i2c; 37 AspeedSCUState scu; 38 AspeedSMCState fmc; 39 AspeedSMCState spi[ASPEED_SPIS_NUM]; 40 AspeedSDMCState sdmc; 41 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 42 FTGMAC100State ftgmac100; 43 } AspeedSoCState; 44 45 #define TYPE_ASPEED_SOC "aspeed-soc" 46 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC) 47 48 typedef struct AspeedSoCInfo { 49 const char *name; 50 const char *cpu_type; 51 uint32_t silicon_rev; 52 hwaddr sdram_base; 53 uint64_t sram_size; 54 int spis_num; 55 const hwaddr *spi_bases; 56 const char *fmc_typename; 57 const char **spi_typename; 58 int wdts_num; 59 } AspeedSoCInfo; 60 61 typedef struct AspeedSoCClass { 62 DeviceClass parent_class; 63 AspeedSoCInfo *info; 64 } AspeedSoCClass; 65 66 #define ASPEED_SOC_CLASS(klass) \ 67 OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC) 68 #define ASPEED_SOC_GET_CLASS(obj) \ 69 OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC) 70 71 #endif /* ASPEED_SOC_H */ 72