1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/misc/aspeed_scu.h" 19 #include "hw/adc/aspeed_adc.h" 20 #include "hw/misc/aspeed_sdmc.h" 21 #include "hw/misc/aspeed_xdma.h" 22 #include "hw/timer/aspeed_timer.h" 23 #include "hw/rtc/aspeed_rtc.h" 24 #include "hw/misc/aspeed_ibt.h" 25 #include "hw/i2c/aspeed_i2c.h" 26 #include "hw/i3c/aspeed_i3c.h" 27 #include "hw/ssi/aspeed_smc.h" 28 #include "hw/misc/aspeed_hace.h" 29 #include "hw/misc/aspeed_sbc.h" 30 #include "hw/misc/aspeed_gfx.h" 31 #include "hw/watchdog/wdt_aspeed.h" 32 #include "hw/net/ftgmac100.h" 33 #include "target/arm/cpu.h" 34 #include "hw/gpio/aspeed_gpio.h" 35 #include "hw/sd/aspeed_sdhci.h" 36 #include "hw/usb/hcd-ehci.h" 37 #include "qom/object.h" 38 #include "hw/misc/aspeed_lpc.h" 39 #include "hw/misc/unimp.h" 40 #include "hw/pci-host/aspeed_pcie.h" 41 #include "hw/misc/aspeed_peci.h" 42 #include "hw/fsi/aspeed-apb2opb.h" 43 #include "hw/misc/aspeed_pwm.h" 44 #include "hw/char/serial.h" 45 46 #define ASPEED_SPIS_NUM 2 47 #define ASPEED_EHCIS_NUM 2 48 #define ASPEED_WDTS_NUM 4 49 #define ASPEED_CPUS_NUM 2 50 #define ASPEED_MACS_NUM 4 51 #define ASPEED_UARTS_NUM 13 52 #define ASPEED_JTAG_NUM 2 53 54 struct AspeedSoCState { 55 DeviceState parent; 56 57 MemoryRegion *memory; 58 MemoryRegion *dram_mr; 59 MemoryRegion dram_container; 60 MemoryRegion sram; 61 MemoryRegion spi_boot_container; 62 MemoryRegion spi_boot; 63 AspeedRtcState rtc; 64 AspeedTimerCtrlState timerctrl; 65 AspeedIBTState ibt; 66 AspeedI2CState i2c; 67 AspeedI3CState i3c; 68 AspeedSCUState scu; 69 AspeedHACEState hace; 70 AspeedXDMAState xdma; 71 AspeedADCState adc; 72 AspeedSMCState fmc; 73 AspeedSMCState spi[ASPEED_SPIS_NUM]; 74 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 75 AspeedSBCState sbc; 76 MemoryRegion secsram; 77 UnimplementedDeviceState sbc_unimplemented; 78 AspeedSDMCState sdmc; 79 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 80 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 81 AspeedMiiState mii[ASPEED_MACS_NUM]; 82 AspeedGPIOState gpio; 83 AspeedGPIOState gpio_1_8v; 84 AspeedSDHCIState sdhci; 85 AspeedSDHCIState emmc; 86 AspeedLPCState lpc; 87 AspeedPCIECfg pcie; 88 AspeedPCIEPhy pcie_phy[2]; 89 AspeedPECIState peci; 90 AspeedGFXState gfx; 91 SerialMM uart[ASPEED_UARTS_NUM]; 92 Clock *sysclk; 93 UnimplementedDeviceState iomem; 94 UnimplementedDeviceState video; 95 UnimplementedDeviceState emmc_boot_controller; 96 UnimplementedDeviceState dpmcu; 97 AspeedPWMState pwm; 98 UnimplementedDeviceState espi; 99 UnimplementedDeviceState udc; 100 UnimplementedDeviceState sgpiom; 101 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; 102 AspeedAPB2OPBState fsi[2]; 103 }; 104 105 #define TYPE_ASPEED_SOC "aspeed-soc" 106 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 107 108 struct Aspeed2400SoCState { 109 AspeedSoCState parent; 110 111 ARMCPU cpu[ASPEED_CPUS_NUM]; 112 AspeedVICState vic; 113 }; 114 115 #define TYPE_ASPEED2400_SOC "aspeed2400-soc" 116 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) 117 118 struct Aspeed2600SoCState { 119 AspeedSoCState parent; 120 121 A15MPPrivState a7mpcore; 122 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */ 123 }; 124 125 #define TYPE_ASPEED2600_SOC "aspeed2600-soc" 126 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) 127 128 struct Aspeed10x0SoCState { 129 AspeedSoCState parent; 130 131 ARMv7MState armv7m; 132 }; 133 134 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" 135 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) 136 137 struct AspeedSoCClass { 138 DeviceClass parent_class; 139 140 const char *name; 141 const char *cpu_type; 142 uint32_t silicon_rev; 143 uint64_t sram_size; 144 uint64_t secsram_size; 145 int spis_num; 146 int ehcis_num; 147 int wdts_num; 148 int macs_num; 149 int uarts_num; 150 const int *irqmap; 151 const hwaddr *memmap; 152 uint32_t num_cpus; 153 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 154 bool boot_emmc; 155 }; 156 157 158 enum { 159 ASPEED_DEV_SPI_BOOT, 160 ASPEED_DEV_IOMEM, 161 ASPEED_DEV_UART1, 162 ASPEED_DEV_UART2, 163 ASPEED_DEV_UART3, 164 ASPEED_DEV_UART4, 165 ASPEED_DEV_UART5, 166 ASPEED_DEV_UART6, 167 ASPEED_DEV_UART7, 168 ASPEED_DEV_UART8, 169 ASPEED_DEV_UART9, 170 ASPEED_DEV_UART10, 171 ASPEED_DEV_UART11, 172 ASPEED_DEV_UART12, 173 ASPEED_DEV_UART13, 174 ASPEED_DEV_VUART, 175 ASPEED_DEV_FMC, 176 ASPEED_DEV_SPI1, 177 ASPEED_DEV_SPI2, 178 ASPEED_DEV_EHCI1, 179 ASPEED_DEV_EHCI2, 180 ASPEED_DEV_VIC, 181 ASPEED_DEV_SDMC, 182 ASPEED_DEV_SCU, 183 ASPEED_DEV_ADC, 184 ASPEED_DEV_SBC, 185 ASPEED_DEV_SECSRAM, 186 ASPEED_DEV_EMMC_BC, 187 ASPEED_DEV_VIDEO, 188 ASPEED_DEV_SRAM, 189 ASPEED_DEV_SDHCI, 190 ASPEED_DEV_GPIO, 191 ASPEED_DEV_GPIO_1_8V, 192 ASPEED_DEV_RTC, 193 ASPEED_DEV_TIMER1, 194 ASPEED_DEV_TIMER2, 195 ASPEED_DEV_TIMER3, 196 ASPEED_DEV_TIMER4, 197 ASPEED_DEV_TIMER5, 198 ASPEED_DEV_TIMER6, 199 ASPEED_DEV_TIMER7, 200 ASPEED_DEV_TIMER8, 201 ASPEED_DEV_WDT, 202 ASPEED_DEV_PWM, 203 ASPEED_DEV_LPC, 204 ASPEED_DEV_IBT, 205 ASPEED_DEV_I2C, 206 ASPEED_DEV_PCIE_PHY1, 207 ASPEED_DEV_PCIE_PHY2, 208 ASPEED_DEV_PCIE, 209 ASPEED_DEV_PCIE_MMIO1, 210 ASPEED_DEV_PCIE_MMIO2, 211 ASPEED_DEV_PECI, 212 ASPEED_DEV_ETH1, 213 ASPEED_DEV_ETH2, 214 ASPEED_DEV_ETH3, 215 ASPEED_DEV_ETH4, 216 ASPEED_DEV_MII1, 217 ASPEED_DEV_MII2, 218 ASPEED_DEV_MII3, 219 ASPEED_DEV_MII4, 220 ASPEED_DEV_SDRAM, 221 ASPEED_DEV_XDMA, 222 ASPEED_DEV_EMMC, 223 ASPEED_DEV_KCS, 224 ASPEED_DEV_HACE, 225 ASPEED_DEV_GFX, 226 ASPEED_DEV_DPMCU, 227 ASPEED_DEV_DP, 228 ASPEED_DEV_I3C, 229 ASPEED_DEV_ESPI, 230 ASPEED_DEV_UDC, 231 ASPEED_DEV_SGPIOM, 232 ASPEED_DEV_JTAG0, 233 ASPEED_DEV_JTAG1, 234 ASPEED_DEV_FSI1, 235 ASPEED_DEV_FSI2, 236 }; 237 238 #define ASPEED_SOC_SPI_BOOT_ADDR 0x0 239 240 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 241 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); 242 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); 243 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 244 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 245 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 246 const char *name, hwaddr addr, 247 uint64_t size); 248 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 249 unsigned int count, int unit0); 250 251 #endif /* ASPEED_SOC_H */ 252