1 /* 2 * ARMv7M CPU object 3 * 4 * Copyright (c) 2017 Linaro Ltd 5 * Written by Peter Maydell <peter.maydell@linaro.org> 6 * 7 * This code is licensed under the GPL version 2 or later. 8 */ 9 10 #ifndef HW_ARM_ARMV7M_H 11 #define HW_ARM_ARMV7M_H 12 13 #include "hw/sysbus.h" 14 #include "hw/intc/armv7m_nvic.h" 15 #include "target/arm/idau.h" 16 #include "qom/object.h" 17 18 #define TYPE_BITBAND "ARM,bitband-memory" 19 typedef struct BitBandState BitBandState; 20 DECLARE_INSTANCE_CHECKER(BitBandState, BITBAND, 21 TYPE_BITBAND) 22 23 struct BitBandState { 24 /*< private >*/ 25 SysBusDevice parent_obj; 26 /*< public >*/ 27 28 AddressSpace source_as; 29 MemoryRegion iomem; 30 uint32_t base; 31 MemoryRegion *source_memory; 32 }; 33 34 #define TYPE_ARMV7M "armv7m" 35 typedef struct ARMv7MState ARMv7MState; 36 DECLARE_INSTANCE_CHECKER(ARMv7MState, ARMV7M, 37 TYPE_ARMV7M) 38 39 #define ARMV7M_NUM_BITBANDS 2 40 41 /* ARMv7M container object. 42 * + Unnamed GPIO input lines: external IRQ lines for the NVIC 43 * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ. 44 * If this GPIO is not wired up then the NVIC will default to performing 45 * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET). 46 * + Property "cpu-type": CPU type to instantiate 47 * + Property "num-irq": number of external IRQ lines 48 * + Property "memory": MemoryRegion defining the physical address space 49 * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal 50 * devices will be automatically layered on top of this view.) 51 * + Property "idau": IDAU interface (forwarded to CPU object) 52 * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object) 53 * + Property "vfp": enable VFP (forwarded to CPU object) 54 * + Property "dsp": enable DSP (forwarded to CPU object) 55 * + Property "enable-bitband": expose bitbanded IO 56 */ 57 struct ARMv7MState { 58 /*< private >*/ 59 SysBusDevice parent_obj; 60 /*< public >*/ 61 NVICState nvic; 62 BitBandState bitband[ARMV7M_NUM_BITBANDS]; 63 ARMCPU *cpu; 64 65 /* MemoryRegion we pass to the CPU, with our devices layered on 66 * top of the ones the board provides in board_memory. 67 */ 68 MemoryRegion container; 69 70 /* Properties */ 71 char *cpu_type; 72 /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ 73 MemoryRegion *board_memory; 74 Object *idau; 75 uint32_t init_svtor; 76 bool enable_bitband; 77 bool start_powered_off; 78 bool vfp; 79 bool dsp; 80 }; 81 82 #endif 83