1 /* 2 * ARMv7M CPU object 3 * 4 * Copyright (c) 2017 Linaro Ltd 5 * Written by Peter Maydell <peter.maydell@linaro.org> 6 * 7 * This code is licensed under the GPL version 2 or later. 8 */ 9 10 #ifndef HW_ARM_ARMV7M_H 11 #define HW_ARM_ARMV7M_H 12 13 #include "hw/sysbus.h" 14 #include "hw/intc/armv7m_nvic.h" 15 #include "hw/misc/armv7m_ras.h" 16 #include "target/arm/idau.h" 17 #include "qom/object.h" 18 #include "hw/clock.h" 19 20 #define TYPE_BITBAND "ARM-bitband-memory" 21 OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND) 22 23 struct BitBandState { 24 /*< private >*/ 25 SysBusDevice parent_obj; 26 /*< public >*/ 27 28 AddressSpace source_as; 29 MemoryRegion iomem; 30 uint32_t base; 31 MemoryRegion *source_memory; 32 }; 33 34 #define TYPE_ARMV7M "armv7m" 35 OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) 36 37 #define ARMV7M_NUM_BITBANDS 2 38 39 /* ARMv7M container object. 40 * + Unnamed GPIO input lines: external IRQ lines for the NVIC 41 * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ. 42 * If this GPIO is not wired up then the NVIC will default to performing 43 * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET). 44 * + Property "cpu-type": CPU type to instantiate 45 * + Property "num-irq": number of external IRQ lines 46 * + Property "memory": MemoryRegion defining the physical address space 47 * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal 48 * devices will be automatically layered on top of this view.) 49 * + Property "idau": IDAU interface (forwarded to CPU object) 50 * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object) 51 * + Property "init-nsvtor": non-secure VTOR reset value (forwarded to CPU object) 52 * + Property "vfp": enable VFP (forwarded to CPU object) 53 * + Property "dsp": enable DSP (forwarded to CPU object) 54 * + Property "enable-bitband": expose bitbanded IO 55 * + Clock input "refclk" is the external reference clock for the systick timers 56 * + Clock input "cpuclk" is the main CPU clock 57 */ 58 struct ARMv7MState { 59 /*< private >*/ 60 SysBusDevice parent_obj; 61 /*< public >*/ 62 NVICState nvic; 63 BitBandState bitband[ARMV7M_NUM_BITBANDS]; 64 ARMCPU *cpu; 65 ARMv7MRAS ras; 66 SysTickState systick[M_REG_NUM_BANKS]; 67 68 /* MemoryRegion we pass to the CPU, with our devices layered on 69 * top of the ones the board provides in board_memory. 70 */ 71 MemoryRegion container; 72 /* 73 * MemoryRegion which passes the transaction to either the S or the 74 * NS systick device depending on the transaction attributes 75 */ 76 MemoryRegion systickmem; 77 /* 78 * MemoryRegion which enforces the S/NS handling of the systick 79 * device NS alias region and passes the transaction to the 80 * NS systick device if appropriate. 81 */ 82 MemoryRegion systick_ns_mem; 83 /* Ditto, for the sysregs region provided by the NVIC */ 84 MemoryRegion sysreg_ns_mem; 85 /* MR providing default PPB behaviour */ 86 MemoryRegion defaultmem; 87 88 Clock *refclk; 89 Clock *cpuclk; 90 91 /* Properties */ 92 char *cpu_type; 93 /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ 94 MemoryRegion *board_memory; 95 Object *idau; 96 uint32_t init_svtor; 97 uint32_t init_nsvtor; 98 bool enable_bitband; 99 bool start_powered_off; 100 bool vfp; 101 bool dsp; 102 }; 103 104 #endif 105