1 /* 2 * ARMv7M CPU object 3 * 4 * Copyright (c) 2017 Linaro Ltd 5 * Written by Peter Maydell <peter.maydell@linaro.org> 6 * 7 * This code is licensed under the GPL version 2 or later. 8 */ 9 10 #ifndef HW_ARM_ARMV7M_H 11 #define HW_ARM_ARMV7M_H 12 13 #include "hw/sysbus.h" 14 #include "hw/intc/armv7m_nvic.h" 15 #include "hw/misc/armv7m_ras.h" 16 #include "target/arm/idau.h" 17 #include "qom/object.h" 18 19 #define TYPE_BITBAND "ARM-bitband-memory" 20 OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND) 21 22 struct BitBandState { 23 /*< private >*/ 24 SysBusDevice parent_obj; 25 /*< public >*/ 26 27 AddressSpace source_as; 28 MemoryRegion iomem; 29 uint32_t base; 30 MemoryRegion *source_memory; 31 }; 32 33 #define TYPE_ARMV7M "armv7m" 34 OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) 35 36 #define ARMV7M_NUM_BITBANDS 2 37 38 /* ARMv7M container object. 39 * + Unnamed GPIO input lines: external IRQ lines for the NVIC 40 * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ. 41 * If this GPIO is not wired up then the NVIC will default to performing 42 * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET). 43 * + Property "cpu-type": CPU type to instantiate 44 * + Property "num-irq": number of external IRQ lines 45 * + Property "memory": MemoryRegion defining the physical address space 46 * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal 47 * devices will be automatically layered on top of this view.) 48 * + Property "idau": IDAU interface (forwarded to CPU object) 49 * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object) 50 * + Property "init-nsvtor": non-secure VTOR reset value (forwarded to CPU object) 51 * + Property "vfp": enable VFP (forwarded to CPU object) 52 * + Property "dsp": enable DSP (forwarded to CPU object) 53 * + Property "enable-bitband": expose bitbanded IO 54 */ 55 struct ARMv7MState { 56 /*< private >*/ 57 SysBusDevice parent_obj; 58 /*< public >*/ 59 NVICState nvic; 60 BitBandState bitband[ARMV7M_NUM_BITBANDS]; 61 ARMCPU *cpu; 62 ARMv7MRAS ras; 63 64 /* MemoryRegion we pass to the CPU, with our devices layered on 65 * top of the ones the board provides in board_memory. 66 */ 67 MemoryRegion container; 68 69 /* Properties */ 70 char *cpu_type; 71 /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ 72 MemoryRegion *board_memory; 73 Object *idau; 74 uint32_t init_svtor; 75 uint32_t init_nsvtor; 76 bool enable_bitband; 77 bool start_powered_off; 78 bool vfp; 79 bool dsp; 80 }; 81 82 #endif 83