1 /* 2 * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * This is a model of the Arm "Subsystems for Embedded" family of 14 * hardware, which include the IoT Kit and the SSE-050, SSE-100 and 15 * SSE-200. Currently we model: 16 * - the Arm IoT Kit which is documented in 17 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 18 * - the SSE-200 which is documented in 19 * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf 20 * 21 * The IoTKit contains: 22 * a Cortex-M33 23 * the IDAU 24 * some timers and watchdogs 25 * two peripheral protection controllers 26 * a memory protection controller 27 * a security controller 28 * a bus fabric which arranges that some parts of the address 29 * space are secure and non-secure aliases of each other 30 * The SSE-200 additionally contains: 31 * a second Cortex-M33 32 * two Message Handling Units (MHUs) 33 * an optional CryptoCell (which we do not model) 34 * more SRAM banks with associated MPCs 35 * multiple Power Policy Units (PPUs) 36 * a control interface for an icache for each CPU 37 * per-CPU identity and control register blocks 38 * 39 * QEMU interface: 40 * + Clock input "MAINCLK": clock for CPUs and most peripherals 41 * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals 42 * + QOM property "memory" is a MemoryRegion containing the devices provided 43 * by the board model. 44 * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock 45 * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. 46 * (In hardware, the SSE-200 permits the number of expansion interrupts 47 * for the two CPUs to be configured separately, but we restrict it to 48 * being the same for both, to avoid having to have separate Property 49 * lists for different variants. This restriction can be relaxed later 50 * if necessary.) 51 * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the 52 * address of each SRAM bank (and thus the total amount of internal SRAM) 53 * + QOM property "init-svtor" sets the initial value of the CPU SVTOR register 54 * (where it expects to load the PC and SP from the vector table on reset) 55 * + QOM properties "CPU0_FPU", "CPU0_DSP", "CPU1_FPU" and "CPU1_DSP" which 56 * set whether the CPUs have the FPU and DSP features present. The default 57 * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an 58 * SSE-200 both are present; CPU0 in an SSE-200 has neither. 59 * Since the IoTKit has only one CPU, it does not have the CPU1_* properties. 60 * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0, 61 * which are wired to its NVIC lines 32 .. n+32 62 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for 63 * CPU 1, which are wired to its NVIC lines 32 .. n+32 64 * + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows 65 * bus master devices in the board model to make transactions into 66 * all the devices and memory areas in the IoTKit 67 * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit 68 * might provide: 69 * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] 70 * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] 71 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable 72 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear 73 * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status 74 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit 75 * might provide: 76 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] 77 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] 78 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable 79 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear 80 * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status 81 * Controlling each of the 16 expansion MPCs which a system using the IoTKit 82 * might provide: 83 * + named GPIO inputs mpcexp_status[0..15] 84 * Controlling each of the 16 expansion MSCs which a system using the IoTKit 85 * might provide: 86 * + named GPIO inputs mscexp_status[0..15] 87 * + named GPIO outputs mscexp_clear[0..15] 88 * + named GPIO outputs mscexp_ns[0..15] 89 */ 90 91 #ifndef ARMSSE_H 92 #define ARMSSE_H 93 94 #include "hw/sysbus.h" 95 #include "hw/arm/armv7m.h" 96 #include "hw/misc/iotkit-secctl.h" 97 #include "hw/misc/tz-ppc.h" 98 #include "hw/misc/tz-mpc.h" 99 #include "hw/timer/cmsdk-apb-timer.h" 100 #include "hw/timer/cmsdk-apb-dualtimer.h" 101 #include "hw/watchdog/cmsdk-apb-watchdog.h" 102 #include "hw/misc/iotkit-sysctl.h" 103 #include "hw/misc/iotkit-sysinfo.h" 104 #include "hw/misc/armsse-cpuid.h" 105 #include "hw/misc/armsse-mhu.h" 106 #include "hw/misc/unimp.h" 107 #include "hw/or-irq.h" 108 #include "hw/clock.h" 109 #include "hw/core/split-irq.h" 110 #include "hw/cpu/cluster.h" 111 #include "qom/object.h" 112 113 #define TYPE_ARM_SSE "arm-sse" 114 OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, 115 ARM_SSE) 116 117 /* 118 * These type names are for specific IoTKit subsystems; other than 119 * instantiating them, code using these devices should always handle 120 * them via the ARMSSE base class, so they have no IOTKIT() etc macros. 121 */ 122 #define TYPE_IOTKIT "iotkit" 123 #define TYPE_SSE200 "sse-200" 124 125 /* We have an IRQ splitter and an OR gate input for each external PPC 126 * and the 2 internal PPCs 127 */ 128 #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) 129 #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) 130 131 #define MAX_SRAM_BANKS 4 132 #if MAX_SRAM_BANKS > IOTS_NUM_MPC 133 #error Too many SRAM banks 134 #endif 135 136 #define SSE_MAX_CPUS 2 137 138 /* These define what each PPU in the ppu[] index is for */ 139 #define CPU0CORE_PPU 0 140 #define CPU1CORE_PPU 1 141 #define DBG_PPU 2 142 #define RAM0_PPU 3 143 #define RAM1_PPU 4 144 #define RAM2_PPU 5 145 #define RAM3_PPU 6 146 #define NUM_PPUS 7 147 148 struct ARMSSE { 149 /*< private >*/ 150 SysBusDevice parent_obj; 151 152 /*< public >*/ 153 ARMv7MState armv7m[SSE_MAX_CPUS]; 154 CPUClusterState cluster[SSE_MAX_CPUS]; 155 IoTKitSecCtl secctl; 156 TZPPC apb_ppc0; 157 TZPPC apb_ppc1; 158 TZMPC mpc[IOTS_NUM_MPC]; 159 CMSDKAPBTimer timer0; 160 CMSDKAPBTimer timer1; 161 CMSDKAPBTimer s32ktimer; 162 qemu_or_irq ppc_irq_orgate; 163 SplitIRQ sec_resp_splitter; 164 SplitIRQ ppc_irq_splitter[NUM_PPCS]; 165 SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC]; 166 qemu_or_irq mpc_irq_orgate; 167 qemu_or_irq nmi_orgate; 168 169 SplitIRQ cpu_irq_splitter[32]; 170 171 CMSDKAPBDualTimer dualtimer; 172 173 CMSDKAPBWatchdog s32kwatchdog; 174 CMSDKAPBWatchdog nswatchdog; 175 CMSDKAPBWatchdog swatchdog; 176 177 IoTKitSysCtl sysctl; 178 IoTKitSysCtl sysinfo; 179 180 ARMSSEMHU mhu[2]; 181 UnimplementedDeviceState ppu[NUM_PPUS]; 182 UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; 183 UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; 184 185 ARMSSECPUID cpuid[SSE_MAX_CPUS]; 186 187 /* 188 * 'container' holds all devices seen by all CPUs. 189 * 'cpu_container[i]' is the view that CPU i has: this has the 190 * per-CPU devices of that CPU, plus as the background 'container' 191 * (or an alias of it, since we can only use it directly once). 192 * container_alias[i] is the alias of 'container' used by CPU i+1; 193 * CPU 0 can use 'container' directly. 194 */ 195 MemoryRegion container; 196 MemoryRegion container_alias[SSE_MAX_CPUS - 1]; 197 MemoryRegion cpu_container[SSE_MAX_CPUS]; 198 MemoryRegion alias1; 199 MemoryRegion alias2; 200 MemoryRegion alias3[SSE_MAX_CPUS]; 201 MemoryRegion sram[MAX_SRAM_BANKS]; 202 203 qemu_irq *exp_irqs[SSE_MAX_CPUS]; 204 qemu_irq ppc0_irq; 205 qemu_irq ppc1_irq; 206 qemu_irq sec_resp_cfg; 207 qemu_irq sec_resp_cfg_in; 208 qemu_irq nsc_cfg_in; 209 210 qemu_irq irq_status_in[NUM_EXTERNAL_PPCS]; 211 qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC]; 212 213 uint32_t nsccfg; 214 215 Clock *mainclk; 216 Clock *s32kclk; 217 218 /* Properties */ 219 MemoryRegion *board_memory; 220 uint32_t exp_numirq; 221 uint32_t mainclk_frq; 222 uint32_t sram_addr_width; 223 uint32_t init_svtor; 224 bool cpu_fpu[SSE_MAX_CPUS]; 225 bool cpu_dsp[SSE_MAX_CPUS]; 226 }; 227 228 typedef struct ARMSSEInfo ARMSSEInfo; 229 230 struct ARMSSEClass { 231 SysBusDeviceClass parent_class; 232 const ARMSSEInfo *info; 233 }; 234 235 236 #endif 237