1 /* 2 * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * This is a model of the Arm "Subsystems for Embedded" family of 14 * hardware, which include the IoT Kit and the SSE-050, SSE-100 and 15 * SSE-200. Currently we model: 16 * - the Arm IoT Kit which is documented in 17 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 18 * - the SSE-200 which is documented in 19 * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf 20 * 21 * The IoTKit contains: 22 * a Cortex-M33 23 * the IDAU 24 * some timers and watchdogs 25 * two peripheral protection controllers 26 * a memory protection controller 27 * a security controller 28 * a bus fabric which arranges that some parts of the address 29 * space are secure and non-secure aliases of each other 30 * The SSE-200 additionally contains: 31 * a second Cortex-M33 32 * two Message Handling Units (MHUs) 33 * an optional CryptoCell (which we do not model) 34 * more SRAM banks with associated MPCs 35 * multiple Power Policy Units (PPUs) 36 * a control interface for an icache for each CPU 37 * per-CPU identity and control register blocks 38 * 39 * QEMU interface: 40 * + QOM property "memory" is a MemoryRegion containing the devices provided 41 * by the board model. 42 * + QOM property "MAINCLK" is the frequency of the main system clock 43 * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. 44 * (In hardware, the SSE-200 permits the number of expansion interrupts 45 * for the two CPUs to be configured separately, but we restrict it to 46 * being the same for both, to avoid having to have separate Property 47 * lists for different variants. This restriction can be relaxed later 48 * if necessary.) 49 * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0, 50 * which are wired to its NVIC lines 32 .. n+32 51 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for 52 * CPU 1, which are wired to its NVIC lines 32 .. n+32 53 * + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows 54 * bus master devices in the board model to make transactions into 55 * all the devices and memory areas in the IoTKit 56 * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit 57 * might provide: 58 * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] 59 * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] 60 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable 61 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear 62 * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status 63 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit 64 * might provide: 65 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] 66 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] 67 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable 68 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear 69 * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status 70 * Controlling each of the 16 expansion MPCs which a system using the IoTKit 71 * might provide: 72 * + named GPIO inputs mpcexp_status[0..15] 73 * Controlling each of the 16 expansion MSCs which a system using the IoTKit 74 * might provide: 75 * + named GPIO inputs mscexp_status[0..15] 76 * + named GPIO outputs mscexp_clear[0..15] 77 * + named GPIO outputs mscexp_ns[0..15] 78 */ 79 80 #ifndef ARMSSE_H 81 #define ARMSSE_H 82 83 #include "hw/sysbus.h" 84 #include "hw/arm/armv7m.h" 85 #include "hw/misc/iotkit-secctl.h" 86 #include "hw/misc/tz-ppc.h" 87 #include "hw/misc/tz-mpc.h" 88 #include "hw/timer/cmsdk-apb-timer.h" 89 #include "hw/timer/cmsdk-apb-dualtimer.h" 90 #include "hw/watchdog/cmsdk-apb-watchdog.h" 91 #include "hw/misc/iotkit-sysctl.h" 92 #include "hw/misc/iotkit-sysinfo.h" 93 #include "hw/misc/armsse-cpuid.h" 94 #include "hw/misc/unimp.h" 95 #include "hw/or-irq.h" 96 #include "hw/core/split-irq.h" 97 #include "hw/cpu/cluster.h" 98 99 #define TYPE_ARMSSE "arm-sse" 100 #define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE) 101 102 /* 103 * These type names are for specific IoTKit subsystems; other than 104 * instantiating them, code using these devices should always handle 105 * them via the ARMSSE base class, so they have no IOTKIT() etc macros. 106 */ 107 #define TYPE_IOTKIT "iotkit" 108 #define TYPE_SSE200 "sse-200" 109 110 /* We have an IRQ splitter and an OR gate input for each external PPC 111 * and the 2 internal PPCs 112 */ 113 #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) 114 #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) 115 116 #define MAX_SRAM_BANKS 4 117 #if MAX_SRAM_BANKS > IOTS_NUM_MPC 118 #error Too many SRAM banks 119 #endif 120 121 #define SSE_MAX_CPUS 2 122 123 /* These define what each PPU in the ppu[] index is for */ 124 #define CPU0CORE_PPU 0 125 #define CPU1CORE_PPU 1 126 #define DBG_PPU 2 127 #define RAM0_PPU 3 128 #define RAM1_PPU 4 129 #define RAM2_PPU 5 130 #define RAM3_PPU 6 131 #define NUM_PPUS 7 132 133 typedef struct ARMSSE { 134 /*< private >*/ 135 SysBusDevice parent_obj; 136 137 /*< public >*/ 138 ARMv7MState armv7m[SSE_MAX_CPUS]; 139 CPUClusterState cluster[SSE_MAX_CPUS]; 140 IoTKitSecCtl secctl; 141 TZPPC apb_ppc0; 142 TZPPC apb_ppc1; 143 TZMPC mpc[IOTS_NUM_MPC]; 144 CMSDKAPBTIMER timer0; 145 CMSDKAPBTIMER timer1; 146 CMSDKAPBTIMER s32ktimer; 147 qemu_or_irq ppc_irq_orgate; 148 SplitIRQ sec_resp_splitter; 149 SplitIRQ ppc_irq_splitter[NUM_PPCS]; 150 SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC]; 151 qemu_or_irq mpc_irq_orgate; 152 qemu_or_irq nmi_orgate; 153 154 SplitIRQ cpu_irq_splitter[32]; 155 156 CMSDKAPBDualTimer dualtimer; 157 158 CMSDKAPBWatchdog s32kwatchdog; 159 CMSDKAPBWatchdog nswatchdog; 160 CMSDKAPBWatchdog swatchdog; 161 162 IoTKitSysCtl sysctl; 163 IoTKitSysCtl sysinfo; 164 165 UnimplementedDeviceState mhu[2]; 166 UnimplementedDeviceState ppu[NUM_PPUS]; 167 UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; 168 UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; 169 170 ARMSSECPUID cpuid[SSE_MAX_CPUS]; 171 172 /* 173 * 'container' holds all devices seen by all CPUs. 174 * 'cpu_container[i]' is the view that CPU i has: this has the 175 * per-CPU devices of that CPU, plus as the background 'container' 176 * (or an alias of it, since we can only use it directly once). 177 * container_alias[i] is the alias of 'container' used by CPU i+1; 178 * CPU 0 can use 'container' directly. 179 */ 180 MemoryRegion container; 181 MemoryRegion container_alias[SSE_MAX_CPUS - 1]; 182 MemoryRegion cpu_container[SSE_MAX_CPUS]; 183 MemoryRegion alias1; 184 MemoryRegion alias2; 185 MemoryRegion alias3; 186 MemoryRegion sram[MAX_SRAM_BANKS]; 187 188 qemu_irq *exp_irqs[SSE_MAX_CPUS]; 189 qemu_irq ppc0_irq; 190 qemu_irq ppc1_irq; 191 qemu_irq sec_resp_cfg; 192 qemu_irq sec_resp_cfg_in; 193 qemu_irq nsc_cfg_in; 194 195 qemu_irq irq_status_in[NUM_EXTERNAL_PPCS]; 196 qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC]; 197 198 uint32_t nsccfg; 199 200 /* Properties */ 201 MemoryRegion *board_memory; 202 uint32_t exp_numirq; 203 uint32_t mainclk_frq; 204 uint32_t sram_addr_width; 205 } ARMSSE; 206 207 typedef struct ARMSSEInfo ARMSSEInfo; 208 209 typedef struct ARMSSEClass { 210 DeviceClass parent_class; 211 const ARMSSEInfo *info; 212 } ARMSSEClass; 213 214 #define ARMSSE_CLASS(klass) \ 215 OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARMSSE) 216 #define ARMSSE_GET_CLASS(obj) \ 217 OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARMSSE) 218 219 #endif 220