16eee5d24SPeter Maydell /* 20829d24eSPeter Maydell * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200 36eee5d24SPeter Maydell * 46eee5d24SPeter Maydell * Copyright (c) 2018 Linaro Limited 56eee5d24SPeter Maydell * Written by Peter Maydell 66eee5d24SPeter Maydell * 76eee5d24SPeter Maydell * This program is free software; you can redistribute it and/or modify 86eee5d24SPeter Maydell * it under the terms of the GNU General Public License version 2 or 96eee5d24SPeter Maydell * (at your option) any later version. 106eee5d24SPeter Maydell */ 116eee5d24SPeter Maydell 126eee5d24SPeter Maydell /* 136eee5d24SPeter Maydell * This is a model of the Arm "Subsystems for Embedded" family of 146eee5d24SPeter Maydell * hardware, which include the IoT Kit and the SSE-050, SSE-100 and 150829d24eSPeter Maydell * SSE-200. Currently we model: 160829d24eSPeter Maydell * - the Arm IoT Kit which is documented in 176eee5d24SPeter Maydell * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 180829d24eSPeter Maydell * - the SSE-200 which is documented in 190829d24eSPeter Maydell * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf 200829d24eSPeter Maydell * 210829d24eSPeter Maydell * The IoTKit contains: 226eee5d24SPeter Maydell * a Cortex-M33 236eee5d24SPeter Maydell * the IDAU 246eee5d24SPeter Maydell * some timers and watchdogs 256eee5d24SPeter Maydell * two peripheral protection controllers 266eee5d24SPeter Maydell * a memory protection controller 276eee5d24SPeter Maydell * a security controller 286eee5d24SPeter Maydell * a bus fabric which arranges that some parts of the address 296eee5d24SPeter Maydell * space are secure and non-secure aliases of each other 300829d24eSPeter Maydell * The SSE-200 additionally contains: 310829d24eSPeter Maydell * a second Cortex-M33 320829d24eSPeter Maydell * two Message Handling Units (MHUs) 330829d24eSPeter Maydell * an optional CryptoCell (which we do not model) 340829d24eSPeter Maydell * more SRAM banks with associated MPCs 350829d24eSPeter Maydell * multiple Power Policy Units (PPUs) 360829d24eSPeter Maydell * a control interface for an icache for each CPU 370829d24eSPeter Maydell * per-CPU identity and control register blocks 386eee5d24SPeter Maydell * 396eee5d24SPeter Maydell * QEMU interface: 406eee5d24SPeter Maydell * + QOM property "memory" is a MemoryRegion containing the devices provided 416eee5d24SPeter Maydell * by the board model. 426eee5d24SPeter Maydell * + QOM property "MAINCLK" is the frequency of the main system clock 4391c1e9fcSPeter Maydell * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. 4491c1e9fcSPeter Maydell * (In hardware, the SSE-200 permits the number of expansion interrupts 4591c1e9fcSPeter Maydell * for the two CPUs to be configured separately, but we restrict it to 4691c1e9fcSPeter Maydell * being the same for both, to avoid having to have separate Property 4791c1e9fcSPeter Maydell * lists for different variants. This restriction can be relaxed later 4891c1e9fcSPeter Maydell * if necessary.) 4974ecf767SPeter Maydell * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the 5074ecf767SPeter Maydell * address of each SRAM bank (and thus the total amount of internal SRAM) 5132187419SPeter Maydell * + QOM property "init-svtor" sets the initial value of the CPU SVTOR register 5232187419SPeter Maydell * (where it expects to load the PC and SP from the vector table on reset) 53a90a862bSPeter Maydell * + QOM properties "CPU0_FPU", "CPU0_DSP", "CPU1_FPU" and "CPU1_DSP" which 54a90a862bSPeter Maydell * set whether the CPUs have the FPU and DSP features present. The default 55a90a862bSPeter Maydell * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an 56a90a862bSPeter Maydell * SSE-200 both are present; CPU0 in an SSE-200 has neither. 57a90a862bSPeter Maydell * Since the IoTKit has only one CPU, it does not have the CPU1_* properties. 5891c1e9fcSPeter Maydell * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0, 5991c1e9fcSPeter Maydell * which are wired to its NVIC lines 32 .. n+32 6091c1e9fcSPeter Maydell * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for 6191c1e9fcSPeter Maydell * CPU 1, which are wired to its NVIC lines 32 .. n+32 626eee5d24SPeter Maydell * + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows 636eee5d24SPeter Maydell * bus master devices in the board model to make transactions into 646eee5d24SPeter Maydell * all the devices and memory areas in the IoTKit 656eee5d24SPeter Maydell * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit 666eee5d24SPeter Maydell * might provide: 676eee5d24SPeter Maydell * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] 686eee5d24SPeter Maydell * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] 696eee5d24SPeter Maydell * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable 706eee5d24SPeter Maydell * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear 716eee5d24SPeter Maydell * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status 726eee5d24SPeter Maydell * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit 736eee5d24SPeter Maydell * might provide: 746eee5d24SPeter Maydell * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] 756eee5d24SPeter Maydell * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] 766eee5d24SPeter Maydell * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable 776eee5d24SPeter Maydell * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear 786eee5d24SPeter Maydell * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status 796eee5d24SPeter Maydell * Controlling each of the 16 expansion MPCs which a system using the IoTKit 806eee5d24SPeter Maydell * might provide: 816eee5d24SPeter Maydell * + named GPIO inputs mpcexp_status[0..15] 826eee5d24SPeter Maydell * Controlling each of the 16 expansion MSCs which a system using the IoTKit 836eee5d24SPeter Maydell * might provide: 846eee5d24SPeter Maydell * + named GPIO inputs mscexp_status[0..15] 856eee5d24SPeter Maydell * + named GPIO outputs mscexp_clear[0..15] 866eee5d24SPeter Maydell * + named GPIO outputs mscexp_ns[0..15] 876eee5d24SPeter Maydell */ 886eee5d24SPeter Maydell 896eee5d24SPeter Maydell #ifndef ARMSSE_H 906eee5d24SPeter Maydell #define ARMSSE_H 916eee5d24SPeter Maydell 926eee5d24SPeter Maydell #include "hw/sysbus.h" 936eee5d24SPeter Maydell #include "hw/arm/armv7m.h" 946eee5d24SPeter Maydell #include "hw/misc/iotkit-secctl.h" 956eee5d24SPeter Maydell #include "hw/misc/tz-ppc.h" 966eee5d24SPeter Maydell #include "hw/misc/tz-mpc.h" 976eee5d24SPeter Maydell #include "hw/timer/cmsdk-apb-timer.h" 986eee5d24SPeter Maydell #include "hw/timer/cmsdk-apb-dualtimer.h" 996eee5d24SPeter Maydell #include "hw/watchdog/cmsdk-apb-watchdog.h" 1006eee5d24SPeter Maydell #include "hw/misc/iotkit-sysctl.h" 1016eee5d24SPeter Maydell #include "hw/misc/iotkit-sysinfo.h" 102ade67dcdSPeter Maydell #include "hw/misc/armsse-cpuid.h" 10368d6b36fSPeter Maydell #include "hw/misc/armsse-mhu.h" 104f8574705SPeter Maydell #include "hw/misc/unimp.h" 1056eee5d24SPeter Maydell #include "hw/or-irq.h" 1066eee5d24SPeter Maydell #include "hw/core/split-irq.h" 1077cd3a2e0SPeter Maydell #include "hw/cpu/cluster.h" 108db1015e9SEduardo Habkost #include "qom/object.h" 1096eee5d24SPeter Maydell 1108055340fSEduardo Habkost #define TYPE_ARM_SSE "arm-sse" 111*c821774aSEduardo Habkost OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, 112*c821774aSEduardo Habkost arm_sse, ARM_SSE) 1136eee5d24SPeter Maydell 1146eee5d24SPeter Maydell /* 1156eee5d24SPeter Maydell * These type names are for specific IoTKit subsystems; other than 1166eee5d24SPeter Maydell * instantiating them, code using these devices should always handle 1176eee5d24SPeter Maydell * them via the ARMSSE base class, so they have no IOTKIT() etc macros. 1186eee5d24SPeter Maydell */ 1196eee5d24SPeter Maydell #define TYPE_IOTKIT "iotkit" 1200829d24eSPeter Maydell #define TYPE_SSE200 "sse-200" 1216eee5d24SPeter Maydell 1226eee5d24SPeter Maydell /* We have an IRQ splitter and an OR gate input for each external PPC 1236eee5d24SPeter Maydell * and the 2 internal PPCs 1246eee5d24SPeter Maydell */ 1256eee5d24SPeter Maydell #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) 1266eee5d24SPeter Maydell #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) 1276eee5d24SPeter Maydell 128f0cab7feSPeter Maydell #define MAX_SRAM_BANKS 4 129f0cab7feSPeter Maydell #if MAX_SRAM_BANKS > IOTS_NUM_MPC 130f0cab7feSPeter Maydell #error Too many SRAM banks 131f0cab7feSPeter Maydell #endif 132f0cab7feSPeter Maydell 13391c1e9fcSPeter Maydell #define SSE_MAX_CPUS 2 13491c1e9fcSPeter Maydell 135e0b00f1bSPeter Maydell /* These define what each PPU in the ppu[] index is for */ 136e0b00f1bSPeter Maydell #define CPU0CORE_PPU 0 137e0b00f1bSPeter Maydell #define CPU1CORE_PPU 1 138e0b00f1bSPeter Maydell #define DBG_PPU 2 139e0b00f1bSPeter Maydell #define RAM0_PPU 3 140e0b00f1bSPeter Maydell #define RAM1_PPU 4 141e0b00f1bSPeter Maydell #define RAM2_PPU 5 142e0b00f1bSPeter Maydell #define RAM3_PPU 6 143e0b00f1bSPeter Maydell #define NUM_PPUS 7 144e0b00f1bSPeter Maydell 145db1015e9SEduardo Habkost struct ARMSSE { 1466eee5d24SPeter Maydell /*< private >*/ 1476eee5d24SPeter Maydell SysBusDevice parent_obj; 1486eee5d24SPeter Maydell 1496eee5d24SPeter Maydell /*< public >*/ 15091c1e9fcSPeter Maydell ARMv7MState armv7m[SSE_MAX_CPUS]; 1517cd3a2e0SPeter Maydell CPUClusterState cluster[SSE_MAX_CPUS]; 1526eee5d24SPeter Maydell IoTKitSecCtl secctl; 1536eee5d24SPeter Maydell TZPPC apb_ppc0; 1546eee5d24SPeter Maydell TZPPC apb_ppc1; 155f0cab7feSPeter Maydell TZMPC mpc[IOTS_NUM_MPC]; 1566eee5d24SPeter Maydell CMSDKAPBTIMER timer0; 1576eee5d24SPeter Maydell CMSDKAPBTIMER timer1; 1586eee5d24SPeter Maydell CMSDKAPBTIMER s32ktimer; 1596eee5d24SPeter Maydell qemu_or_irq ppc_irq_orgate; 1606eee5d24SPeter Maydell SplitIRQ sec_resp_splitter; 1616eee5d24SPeter Maydell SplitIRQ ppc_irq_splitter[NUM_PPCS]; 1626eee5d24SPeter Maydell SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC]; 1636eee5d24SPeter Maydell qemu_or_irq mpc_irq_orgate; 1646eee5d24SPeter Maydell qemu_or_irq nmi_orgate; 1656eee5d24SPeter Maydell 16691c1e9fcSPeter Maydell SplitIRQ cpu_irq_splitter[32]; 16791c1e9fcSPeter Maydell 1686eee5d24SPeter Maydell CMSDKAPBDualTimer dualtimer; 1696eee5d24SPeter Maydell 1706eee5d24SPeter Maydell CMSDKAPBWatchdog s32kwatchdog; 1716eee5d24SPeter Maydell CMSDKAPBWatchdog nswatchdog; 1726eee5d24SPeter Maydell CMSDKAPBWatchdog swatchdog; 1736eee5d24SPeter Maydell 1746eee5d24SPeter Maydell IoTKitSysCtl sysctl; 1756eee5d24SPeter Maydell IoTKitSysCtl sysinfo; 1766eee5d24SPeter Maydell 17768d6b36fSPeter Maydell ARMSSEMHU mhu[2]; 178e0b00f1bSPeter Maydell UnimplementedDeviceState ppu[NUM_PPUS]; 1792357bca5SPeter Maydell UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; 180c1f57257SPeter Maydell UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; 181f8574705SPeter Maydell 182ade67dcdSPeter Maydell ARMSSECPUID cpuid[SSE_MAX_CPUS]; 183ade67dcdSPeter Maydell 184d847ca51SPeter Maydell /* 185d847ca51SPeter Maydell * 'container' holds all devices seen by all CPUs. 186d847ca51SPeter Maydell * 'cpu_container[i]' is the view that CPU i has: this has the 187d847ca51SPeter Maydell * per-CPU devices of that CPU, plus as the background 'container' 188d847ca51SPeter Maydell * (or an alias of it, since we can only use it directly once). 189d847ca51SPeter Maydell * container_alias[i] is the alias of 'container' used by CPU i+1; 190d847ca51SPeter Maydell * CPU 0 can use 'container' directly. 191d847ca51SPeter Maydell */ 1926eee5d24SPeter Maydell MemoryRegion container; 193d847ca51SPeter Maydell MemoryRegion container_alias[SSE_MAX_CPUS - 1]; 194d847ca51SPeter Maydell MemoryRegion cpu_container[SSE_MAX_CPUS]; 1956eee5d24SPeter Maydell MemoryRegion alias1; 1966eee5d24SPeter Maydell MemoryRegion alias2; 1973733f803SPeter Maydell MemoryRegion alias3[SSE_MAX_CPUS]; 198f0cab7feSPeter Maydell MemoryRegion sram[MAX_SRAM_BANKS]; 1996eee5d24SPeter Maydell 20091c1e9fcSPeter Maydell qemu_irq *exp_irqs[SSE_MAX_CPUS]; 2016eee5d24SPeter Maydell qemu_irq ppc0_irq; 2026eee5d24SPeter Maydell qemu_irq ppc1_irq; 2036eee5d24SPeter Maydell qemu_irq sec_resp_cfg; 2046eee5d24SPeter Maydell qemu_irq sec_resp_cfg_in; 2056eee5d24SPeter Maydell qemu_irq nsc_cfg_in; 2066eee5d24SPeter Maydell 2076eee5d24SPeter Maydell qemu_irq irq_status_in[NUM_EXTERNAL_PPCS]; 2086eee5d24SPeter Maydell qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC]; 2096eee5d24SPeter Maydell 2106eee5d24SPeter Maydell uint32_t nsccfg; 2116eee5d24SPeter Maydell 2126eee5d24SPeter Maydell /* Properties */ 2136eee5d24SPeter Maydell MemoryRegion *board_memory; 2146eee5d24SPeter Maydell uint32_t exp_numirq; 2156eee5d24SPeter Maydell uint32_t mainclk_frq; 2164b635cf7SPeter Maydell uint32_t sram_addr_width; 21732187419SPeter Maydell uint32_t init_svtor; 218a90a862bSPeter Maydell bool cpu_fpu[SSE_MAX_CPUS]; 219a90a862bSPeter Maydell bool cpu_dsp[SSE_MAX_CPUS]; 220db1015e9SEduardo Habkost }; 2216eee5d24SPeter Maydell 2226eee5d24SPeter Maydell typedef struct ARMSSEInfo ARMSSEInfo; 2236eee5d24SPeter Maydell 224db1015e9SEduardo Habkost struct ARMSSEClass { 225512c65e6SEduardo Habkost SysBusDeviceClass parent_class; 2266eee5d24SPeter Maydell const ARMSSEInfo *info; 227db1015e9SEduardo Habkost }; 2286eee5d24SPeter Maydell 2296eee5d24SPeter Maydell 2306eee5d24SPeter Maydell #endif 231