1 /* 2 * Allwinner R40/A40i/T3 System on Chip emulation 3 * 4 * Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HW_ARM_ALLWINNER_R40_H 21 #define HW_ARM_ALLWINNER_R40_H 22 23 #include "qom/object.h" 24 #include "hw/arm/boot.h" 25 #include "hw/timer/allwinner-a10-pit.h" 26 #include "hw/intc/arm_gic.h" 27 #include "hw/sd/allwinner-sdhost.h" 28 #include "hw/misc/allwinner-r40-ccu.h" 29 #include "hw/misc/allwinner-r40-dramc.h" 30 #include "hw/misc/allwinner-sramc.h" 31 #include "hw/i2c/allwinner-i2c.h" 32 #include "hw/net/allwinner_emac.h" 33 #include "hw/net/allwinner-sun8i-emac.h" 34 #include "target/arm/cpu.h" 35 #include "sysemu/block-backend.h" 36 37 enum { 38 AW_R40_DEV_SRAM_A1, 39 AW_R40_DEV_SRAM_A2, 40 AW_R40_DEV_SRAM_A3, 41 AW_R40_DEV_SRAM_A4, 42 AW_R40_DEV_SRAMC, 43 AW_R40_DEV_EMAC, 44 AW_R40_DEV_MMC0, 45 AW_R40_DEV_MMC1, 46 AW_R40_DEV_MMC2, 47 AW_R40_DEV_MMC3, 48 AW_R40_DEV_CCU, 49 AW_R40_DEV_PIT, 50 AW_R40_DEV_UART0, 51 AW_R40_DEV_UART1, 52 AW_R40_DEV_UART2, 53 AW_R40_DEV_UART3, 54 AW_R40_DEV_UART4, 55 AW_R40_DEV_UART5, 56 AW_R40_DEV_UART6, 57 AW_R40_DEV_UART7, 58 AW_R40_DEV_TWI0, 59 AW_R40_DEV_GMAC, 60 AW_R40_DEV_GIC_DIST, 61 AW_R40_DEV_GIC_CPU, 62 AW_R40_DEV_GIC_HYP, 63 AW_R40_DEV_GIC_VCPU, 64 AW_R40_DEV_SDRAM, 65 AW_R40_DEV_DRAMCOM, 66 AW_R40_DEV_DRAMCTL, 67 AW_R40_DEV_DRAMPHY, 68 }; 69 70 #define AW_R40_NUM_CPUS (4) 71 72 /** 73 * Allwinner R40 object model 74 * @{ 75 */ 76 77 /** Object type for the Allwinner R40 SoC */ 78 #define TYPE_AW_R40 "allwinner-r40" 79 80 /** Convert input object to Allwinner R40 state object */ 81 OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40) 82 83 /** @} */ 84 85 /** 86 * Allwinner R40 object 87 * 88 * This struct contains the state of all the devices 89 * which are currently emulated by the R40 SoC code. 90 */ 91 #define AW_R40_NUM_MMCS 4 92 #define AW_R40_NUM_UARTS 8 93 94 struct AwR40State { 95 /*< private >*/ 96 DeviceState parent_obj; 97 /*< public >*/ 98 99 /** Physical base address for start of RAM */ 100 hwaddr ram_addr; 101 102 /** Total RAM size in megabytes */ 103 uint32_t ram_size; 104 105 ARMCPU cpus[AW_R40_NUM_CPUS]; 106 const hwaddr *memmap; 107 AwSRAMCState sramc; 108 AwA10PITState timer; 109 AwSdHostState mmc[AW_R40_NUM_MMCS]; 110 AwR40ClockCtlState ccu; 111 AwR40DramCtlState dramc; 112 AWI2CState i2c0; 113 AwEmacState emac; 114 AwSun8iEmacState gmac; 115 GICState gic; 116 MemoryRegion sram_a1; 117 MemoryRegion sram_a2; 118 MemoryRegion sram_a3; 119 MemoryRegion sram_a4; 120 }; 121 122 /** 123 * Emulate Boot ROM firmware setup functionality. 124 * 125 * A real Allwinner R40 SoC contains a Boot ROM 126 * which is the first code that runs right after 127 * the SoC is powered on. The Boot ROM is responsible 128 * for loading user code (e.g. a bootloader) from any 129 * of the supported external devices and writing the 130 * downloaded code to internal SRAM. After loading the SoC 131 * begins executing the code written to SRAM. 132 * 133 * This function emulates the Boot ROM by copying 32 KiB 134 * of data from the given block device and writes it to 135 * the start of the first internal SRAM memory. 136 * 137 * @s: Allwinner R40 state object pointer 138 * @blk: Block backend device object pointer 139 * @unit: the mmc control's unit 140 */ 141 bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int unit); 142 143 #endif /* HW_ARM_ALLWINNER_R40_H */ 144