10553d895SMarkus Armbruster #ifndef HW_ARM_ALLWINNER_A10_H 20553d895SMarkus Armbruster #define HW_ARM_ALLWINNER_A10_H 39158fa54Sliguang 49158fa54Sliguang #include "qemu/error-report.h" 59158fa54Sliguang #include "hw/char/serial.h" 612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 7edf5ca5dSMarkus Armbruster #include "hw/pci/pci_device.h" 89158fa54Sliguang #include "hw/timer/allwinner-a10-pit.h" 99158fa54Sliguang #include "hw/intc/allwinner-a10-pic.h" 10db7dfd4cSBeniamino Galvani #include "hw/net/allwinner_emac.h" 1182e48382SNiek Linnenbank #include "hw/sd/allwinner-sdhost.h" 12dca62576SPeter Crosthwaite #include "hw/ide/ahci.h" 137abc8cabSGuenter Roeck #include "hw/usb/hcd-ohci.h" 147abc8cabSGuenter Roeck #include "hw/usb/hcd-ehci.h" 15a9ad9e73SNiek Linnenbank #include "hw/rtc/allwinner-rtc.h" 16423ec28bSStrahinja Jankovic #include "hw/misc/allwinner-a10-ccm.h" 17edd3a59dSStrahinja Jankovic #include "hw/misc/allwinner-a10-dramc.h" 189be8a82cSStrahinja Jankovic #include "hw/i2c/allwinner-i2c.h" 19*bb9271caSStrahinja Jankovic #include "sysemu/block-backend.h" 209158fa54Sliguang 21ec150c7eSMarkus Armbruster #include "target/arm/cpu.h" 22db1015e9SEduardo Habkost #include "qom/object.h" 239158fa54Sliguang 249158fa54Sliguang 259158fa54Sliguang #define AW_A10_SDRAM_BASE 0x40000000 269158fa54Sliguang 277abc8cabSGuenter Roeck #define AW_A10_NUM_USB 2 287abc8cabSGuenter Roeck 299158fa54Sliguang #define TYPE_AW_A10 "allwinner-a10" 308063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(AwA10State, AW_A10) 319158fa54Sliguang 32db1015e9SEduardo Habkost struct AwA10State { 339158fa54Sliguang /*< private >*/ 349158fa54Sliguang DeviceState parent_obj; 359158fa54Sliguang /*< public >*/ 369158fa54Sliguang 379158fa54Sliguang ARMCPU cpu; 38423ec28bSStrahinja Jankovic AwA10ClockCtlState ccm; 39edd3a59dSStrahinja Jankovic AwA10DramControllerState dramc; 409158fa54Sliguang AwA10PITState timer; 419158fa54Sliguang AwA10PICState intc; 42db7dfd4cSBeniamino Galvani AwEmacState emac; 43dca62576SPeter Crosthwaite AllwinnerAHCIState sata; 4482e48382SNiek Linnenbank AwSdHostState mmc0; 459be8a82cSStrahinja Jankovic AWI2CState i2c0; 46a9ad9e73SNiek Linnenbank AwRtcState rtc; 47ead07aa4SPhilippe Mathieu-Daudé MemoryRegion sram_a; 487abc8cabSGuenter Roeck EHCISysBusState ehci[AW_A10_NUM_USB]; 497abc8cabSGuenter Roeck OHCISysBusState ohci[AW_A10_NUM_USB]; 50db1015e9SEduardo Habkost }; 519158fa54Sliguang 52*bb9271caSStrahinja Jankovic /** 53*bb9271caSStrahinja Jankovic * Emulate Boot ROM firmware setup functionality. 54*bb9271caSStrahinja Jankovic * 55*bb9271caSStrahinja Jankovic * A real Allwinner A10 SoC contains a Boot ROM 56*bb9271caSStrahinja Jankovic * which is the first code that runs right after 57*bb9271caSStrahinja Jankovic * the SoC is powered on. The Boot ROM is responsible 58*bb9271caSStrahinja Jankovic * for loading user code (e.g. a bootloader) from any 59*bb9271caSStrahinja Jankovic * of the supported external devices and writing the 60*bb9271caSStrahinja Jankovic * downloaded code to internal SRAM. After loading the SoC 61*bb9271caSStrahinja Jankovic * begins executing the code written to SRAM. 62*bb9271caSStrahinja Jankovic * 63*bb9271caSStrahinja Jankovic * This function emulates the Boot ROM by copying 32 KiB 64*bb9271caSStrahinja Jankovic * of data at offset 8 KiB from the given block device and writes it to 65*bb9271caSStrahinja Jankovic * the start of the first internal SRAM memory. 66*bb9271caSStrahinja Jankovic * 67*bb9271caSStrahinja Jankovic * @s: Allwinner A10 state object pointer 68*bb9271caSStrahinja Jankovic * @blk: Block backend device object pointer 69*bb9271caSStrahinja Jankovic */ 70*bb9271caSStrahinja Jankovic void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk); 71*bb9271caSStrahinja Jankovic 729158fa54Sliguang #endif 73