xref: /openbmc/qemu/include/hw/adc/max111x.h (revision 57e28d34)
1*58f3e3feSCorey Minyard /*
2*58f3e3feSCorey Minyard  * Maxim MAX1110/1111 ADC chip emulation.
3*58f3e3feSCorey Minyard  *
4*58f3e3feSCorey Minyard  * Copyright (c) 2006 Openedhand Ltd.
5*58f3e3feSCorey Minyard  * Written by Andrzej Zaborowski <balrog@zabor.org>
6*58f3e3feSCorey Minyard  *
7*58f3e3feSCorey Minyard  * This code is licensed under the GNU GPLv2.
8*58f3e3feSCorey Minyard  *
9*58f3e3feSCorey Minyard  * Contributions after 2012-01-13 are licensed under the terms of the
10*58f3e3feSCorey Minyard  * GNU GPL, version 2 or (at your option) any later version.
11*58f3e3feSCorey Minyard  */
12*58f3e3feSCorey Minyard 
13*58f3e3feSCorey Minyard #ifndef HW_MISC_MAX111X_H
14*58f3e3feSCorey Minyard #define HW_MISC_MAX111X_H
15*58f3e3feSCorey Minyard 
16*58f3e3feSCorey Minyard #include "hw/ssi/ssi.h"
17*58f3e3feSCorey Minyard #include "qom/object.h"
18*58f3e3feSCorey Minyard 
19*58f3e3feSCorey Minyard /*
20*58f3e3feSCorey Minyard  * This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU
21*58f3e3feSCorey Minyard  * is an SSI slave device. It has either 4 (max1110) or 8 (max1111)
22*58f3e3feSCorey Minyard  * 8-bit ADC channels.
23*58f3e3feSCorey Minyard  *
24*58f3e3feSCorey Minyard  * QEMU interface:
25*58f3e3feSCorey Minyard  *  + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value
26*58f3e3feSCorey Minyard  *    of each ADC input, as an unsigned 8-bit value
27*58f3e3feSCorey Minyard  *  + GPIO output 0: interrupt line
28*58f3e3feSCorey Minyard  *  + Properties "input0" to "input3" (max1110) or "input0" to "input7"
29*58f3e3feSCorey Minyard  *    (max1111): initial reset values for ADC inputs.
30*58f3e3feSCorey Minyard  *
31*58f3e3feSCorey Minyard  * Known bugs:
32*58f3e3feSCorey Minyard  *  + the interrupt line is not correctly implemented, and will never
33*58f3e3feSCorey Minyard  *    be lowered once it has been asserted.
34*58f3e3feSCorey Minyard  */
35*58f3e3feSCorey Minyard struct MAX111xState {
36*58f3e3feSCorey Minyard     SSIPeripheral parent_obj;
37*58f3e3feSCorey Minyard 
38*58f3e3feSCorey Minyard     qemu_irq interrupt;
39*58f3e3feSCorey Minyard     /* Values of inputs at system reset (settable by QOM property) */
40*58f3e3feSCorey Minyard     uint8_t reset_input[8];
41*58f3e3feSCorey Minyard 
42*58f3e3feSCorey Minyard     uint8_t tb1, rb2, rb3;
43*58f3e3feSCorey Minyard     int cycle;
44*58f3e3feSCorey Minyard 
45*58f3e3feSCorey Minyard     uint8_t input[8];
46*58f3e3feSCorey Minyard     int inputs, com;
47*58f3e3feSCorey Minyard };
48*58f3e3feSCorey Minyard 
49*58f3e3feSCorey Minyard #define TYPE_MAX_111X "max111x"
50*58f3e3feSCorey Minyard 
51*58f3e3feSCorey Minyard OBJECT_DECLARE_SIMPLE_TYPE(MAX111xState, MAX_111X)
52*58f3e3feSCorey Minyard 
53*58f3e3feSCorey Minyard #define TYPE_MAX_1110 "max1110"
54*58f3e3feSCorey Minyard #define TYPE_MAX_1111 "max1111"
55*58f3e3feSCorey Minyard 
56*58f3e3feSCorey Minyard #endif
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