xref: /openbmc/qemu/include/hw/adc/aspeed_adc.h (revision 2d1bf258)
1 /*
2  * Aspeed ADC
3  *
4  * Copyright 2017-2021 IBM Corp.
5  *
6  * Andrew Jeffery <andrew@aj.id.au>
7  *
8  * SPDX-License-Identifier: GPL-2.0-or-later
9  */
10 
11 #ifndef HW_ADC_ASPEED_ADC_H
12 #define HW_ADC_ASPEED_ADC_H
13 
14 #include "hw/sysbus.h"
15 
16 #define TYPE_ASPEED_ADC "aspeed.adc"
17 #define TYPE_ASPEED_2400_ADC TYPE_ASPEED_ADC "-ast2400"
18 #define TYPE_ASPEED_2500_ADC TYPE_ASPEED_ADC "-ast2500"
19 #define TYPE_ASPEED_2600_ADC TYPE_ASPEED_ADC "-ast2600"
20 #define TYPE_ASPEED_1030_ADC TYPE_ASPEED_ADC "-ast1030"
21 #define TYPE_ASPEED_2700_ADC TYPE_ASPEED_ADC "-ast2700"
22 OBJECT_DECLARE_TYPE(AspeedADCState, AspeedADCClass, ASPEED_ADC)
23 
24 #define TYPE_ASPEED_ADC_ENGINE "aspeed.adc.engine"
25 OBJECT_DECLARE_SIMPLE_TYPE(AspeedADCEngineState, ASPEED_ADC_ENGINE)
26 
27 #define ASPEED_ADC_NR_CHANNELS 16
28 #define ASPEED_ADC_NR_REGS     (0xD0 >> 2)
29 
30 struct AspeedADCEngineState {
31     /* <private> */
32     SysBusDevice parent;
33 
34     MemoryRegion mmio;
35     qemu_irq irq;
36     uint32_t engine_id;
37     uint32_t nr_channels;
38     uint32_t regs[ASPEED_ADC_NR_REGS];
39 };
40 
41 struct AspeedADCState {
42     /* <private> */
43     SysBusDevice parent;
44 
45     MemoryRegion mmio;
46     qemu_irq irq;
47 
48     AspeedADCEngineState engines[2];
49 };
50 
51 struct AspeedADCClass {
52     SysBusDeviceClass parent_class;
53 
54     uint32_t nr_engines;
55 };
56 
57 #endif /* HW_ADC_ASPEED_ADC_H */
58