xref: /openbmc/qemu/include/hw/acpi/tpm.h (revision fe29141b)
1 /*
2  * tpm.h - TPM ACPI definitions
3  *
4  * Copyright (C) 2014 IBM Corporation
5  *
6  * Authors:
7  *  Stefan Berger <stefanb@us.ibm.com>
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  *
12  * Implementation of the TIS interface according to specs found at
13  * http://www.trustedcomputinggroup.org
14  *
15  */
16 #ifndef HW_ACPI_TPM_H
17 #define HW_ACPI_TPM_H
18 
19 #include "hw/registerfields.h"
20 
21 #define TPM_TIS_ADDR_BASE           0xFED40000
22 #define TPM_TIS_ADDR_SIZE           0x5000
23 
24 #define TPM_TIS_IRQ                 5
25 
26 REG32(CRB_LOC_STATE, 0x00)
27   FIELD(CRB_LOC_STATE, tpmEstablished, 0, 1)
28   FIELD(CRB_LOC_STATE, locAssigned, 1, 1)
29   FIELD(CRB_LOC_STATE, activeLocality, 2, 3)
30   FIELD(CRB_LOC_STATE, reserved, 5, 2)
31   FIELD(CRB_LOC_STATE, tpmRegValidSts, 7, 1)
32 REG32(CRB_LOC_CTRL, 0x08)
33 REG32(CRB_LOC_STS, 0x0C)
34   FIELD(CRB_LOC_STS, Granted, 0, 1)
35   FIELD(CRB_LOC_STS, beenSeized, 1, 1)
36 REG32(CRB_INTF_ID, 0x30)
37   FIELD(CRB_INTF_ID, InterfaceType, 0, 4)
38   FIELD(CRB_INTF_ID, InterfaceVersion, 4, 4)
39   FIELD(CRB_INTF_ID, CapLocality, 8, 1)
40   FIELD(CRB_INTF_ID, CapCRBIdleBypass, 9, 1)
41   FIELD(CRB_INTF_ID, Reserved1, 10, 1)
42   FIELD(CRB_INTF_ID, CapDataXferSizeSupport, 11, 2)
43   FIELD(CRB_INTF_ID, CapFIFO, 13, 1)
44   FIELD(CRB_INTF_ID, CapCRB, 14, 1)
45   FIELD(CRB_INTF_ID, CapIFRes, 15, 2)
46   FIELD(CRB_INTF_ID, InterfaceSelector, 17, 2)
47   FIELD(CRB_INTF_ID, IntfSelLock, 19, 1)
48   FIELD(CRB_INTF_ID, Reserved2, 20, 4)
49   FIELD(CRB_INTF_ID, RID, 24, 8)
50 REG32(CRB_INTF_ID2, 0x34)
51   FIELD(CRB_INTF_ID2, VID, 0, 16)
52   FIELD(CRB_INTF_ID2, DID, 16, 16)
53 REG32(CRB_CTRL_EXT, 0x38)
54 REG32(CRB_CTRL_REQ, 0x40)
55 REG32(CRB_CTRL_STS, 0x44)
56   FIELD(CRB_CTRL_STS, tpmSts, 0, 1)
57   FIELD(CRB_CTRL_STS, tpmIdle, 1, 1)
58 REG32(CRB_CTRL_CANCEL, 0x48)
59 REG32(CRB_CTRL_START, 0x4C)
60 REG32(CRB_INT_ENABLED, 0x50)
61 REG32(CRB_INT_STS, 0x54)
62 REG32(CRB_CTRL_CMD_SIZE, 0x58)
63 REG32(CRB_CTRL_CMD_LADDR, 0x5C)
64 REG32(CRB_CTRL_CMD_HADDR, 0x60)
65 REG32(CRB_CTRL_RSP_SIZE, 0x64)
66 REG32(CRB_CTRL_RSP_ADDR, 0x68)
67 REG32(CRB_DATA_BUFFER, 0x80)
68 
69 #define TPM_CRB_ADDR_BASE           0xFED40000
70 #define TPM_CRB_ADDR_SIZE           0x1000
71 #define TPM_CRB_ADDR_CTRL           (TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ)
72 #define TPM_CRB_R_MAX               R_CRB_DATA_BUFFER
73 
74 #define TPM_LOG_AREA_MINIMUM_SIZE   (64 * 1024)
75 
76 #define TPM_TCPA_ACPI_CLASS_CLIENT  0
77 #define TPM_TCPA_ACPI_CLASS_SERVER  1
78 
79 #define TPM2_ACPI_CLASS_CLIENT      0
80 #define TPM2_ACPI_CLASS_SERVER      1
81 
82 #define TPM2_START_METHOD_MMIO      6
83 #define TPM2_START_METHOD_CRB       7
84 
85 #endif /* HW_ACPI_TPM_H */
86