1 /* 2 * tpm.h - TPM ACPI definitions 3 * 4 * Copyright (C) 2014 IBM Corporation 5 * 6 * Authors: 7 * Stefan Berger <stefanb@us.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * Implementation of the TIS interface according to specs found at 13 * http://www.trustedcomputinggroup.org 14 * 15 */ 16 #ifndef HW_ACPI_TPM_H 17 #define HW_ACPI_TPM_H 18 19 #include "qemu/units.h" 20 #include "hw/registerfields.h" 21 #include "hw/acpi/aml-build.h" 22 #include "sysemu/tpm.h" 23 24 #ifdef CONFIG_TPM 25 26 #define TPM_TIS_ADDR_BASE 0xFED40000 27 #define TPM_TIS_ADDR_SIZE 0x5000 28 29 #define TPM_TIS_IRQ 5 30 31 #define TPM_TIS_NUM_LOCALITIES 5 /* per spec */ 32 #define TPM_TIS_LOCALITY_SHIFT 12 33 34 /* tis registers */ 35 #define TPM_TIS_REG_ACCESS 0x00 36 #define TPM_TIS_REG_INT_ENABLE 0x08 37 #define TPM_TIS_REG_INT_VECTOR 0x0c 38 #define TPM_TIS_REG_INT_STATUS 0x10 39 #define TPM_TIS_REG_INTF_CAPABILITY 0x14 40 #define TPM_TIS_REG_STS 0x18 41 #define TPM_TIS_REG_DATA_FIFO 0x24 42 #define TPM_TIS_REG_INTERFACE_ID 0x30 43 #define TPM_TIS_REG_DATA_XFIFO 0x80 44 #define TPM_TIS_REG_DATA_XFIFO_END 0xbc 45 #define TPM_TIS_REG_DID_VID 0xf00 46 #define TPM_TIS_REG_RID 0xf04 47 48 /* vendor-specific registers */ 49 #define TPM_TIS_REG_DEBUG 0xf90 50 51 #define TPM_TIS_STS_TPM_FAMILY_MASK (0x3 << 26)/* TPM 2.0 */ 52 #define TPM_TIS_STS_TPM_FAMILY1_2 (0 << 26) /* TPM 2.0 */ 53 #define TPM_TIS_STS_TPM_FAMILY2_0 (1 << 26) /* TPM 2.0 */ 54 #define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25) /* TPM 2.0 */ 55 #define TPM_TIS_STS_COMMAND_CANCEL (1 << 24) /* TPM 2.0 */ 56 57 #define TPM_TIS_STS_VALID (1 << 7) 58 #define TPM_TIS_STS_COMMAND_READY (1 << 6) 59 #define TPM_TIS_STS_TPM_GO (1 << 5) 60 #define TPM_TIS_STS_DATA_AVAILABLE (1 << 4) 61 #define TPM_TIS_STS_EXPECT (1 << 3) 62 #define TPM_TIS_STS_SELFTEST_DONE (1 << 2) 63 #define TPM_TIS_STS_RESPONSE_RETRY (1 << 1) 64 65 #define TPM_TIS_BURST_COUNT_SHIFT 8 66 #define TPM_TIS_BURST_COUNT(X) \ 67 ((X) << TPM_TIS_BURST_COUNT_SHIFT) 68 69 #define TPM_TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) 70 #define TPM_TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) 71 #define TPM_TIS_ACCESS_BEEN_SEIZED (1 << 4) 72 #define TPM_TIS_ACCESS_SEIZE (1 << 3) 73 #define TPM_TIS_ACCESS_PENDING_REQUEST (1 << 2) 74 #define TPM_TIS_ACCESS_REQUEST_USE (1 << 1) 75 #define TPM_TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) 76 77 #define TPM_TIS_INT_ENABLED (1 << 31) 78 #define TPM_TIS_INT_DATA_AVAILABLE (1 << 0) 79 #define TPM_TIS_INT_STS_VALID (1 << 1) 80 #define TPM_TIS_INT_LOCALITY_CHANGED (1 << 2) 81 #define TPM_TIS_INT_COMMAND_READY (1 << 7) 82 83 #define TPM_TIS_INT_POLARITY_MASK (3 << 3) 84 #define TPM_TIS_INT_POLARITY_LOW_LEVEL (1 << 3) 85 86 #define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \ 87 TPM_TIS_INT_DATA_AVAILABLE | \ 88 TPM_TIS_INT_STS_VALID | \ 89 TPM_TIS_INT_COMMAND_READY) 90 91 #define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28) 92 #define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28) 93 #define TPM_TIS_CAP_DATA_TRANSFER_64B (3 << 9) 94 #define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9) 95 #define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8) 96 #define TPM_TIS_CAP_BURST_COUNT_STATIC (1 << 8) 97 #define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL (1 << 4) /* support is mandatory */ 98 #define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \ 99 (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ 100 TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ 101 TPM_TIS_CAP_DATA_TRANSFER_64B | \ 102 TPM_TIS_CAP_INTERFACE_VERSION1_3 | \ 103 TPM_TIS_INTERRUPTS_SUPPORTED) 104 105 #define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \ 106 (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ 107 TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ 108 TPM_TIS_CAP_DATA_TRANSFER_64B | \ 109 TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \ 110 TPM_TIS_INTERRUPTS_SUPPORTED) 111 112 #define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 (0xf) /* TPM 2.0 */ 113 #define TPM_TIS_IFACE_ID_INTERFACE_FIFO (0x0) /* TPM 2.0 */ 114 #define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4) /* TPM 2.0 */ 115 #define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES (1 << 8) /* TPM 2.0 */ 116 #define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED (1 << 13) /* TPM 2.0 */ 117 #define TPM_TIS_IFACE_ID_INT_SEL_LOCK (1 << 19) /* TPM 2.0 */ 118 119 #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \ 120 (TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \ 121 (~0u << 4)/* all of it is don't care */) 122 123 /* if backend was a TPM 2.0: */ 124 #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \ 125 (TPM_TIS_IFACE_ID_INTERFACE_FIFO | \ 126 TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \ 127 TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \ 128 TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED) 129 130 #define TPM_TIS_TPM_DID 0x0001 131 #define TPM_TIS_TPM_VID PCI_VENDOR_ID_IBM 132 #define TPM_TIS_TPM_RID 0x0001 133 134 #define TPM_TIS_NO_DATA_BYTE 0xff 135 136 137 REG32(CRB_LOC_STATE, 0x00) 138 FIELD(CRB_LOC_STATE, tpmEstablished, 0, 1) 139 FIELD(CRB_LOC_STATE, locAssigned, 1, 1) 140 FIELD(CRB_LOC_STATE, activeLocality, 2, 3) 141 FIELD(CRB_LOC_STATE, reserved, 5, 2) 142 FIELD(CRB_LOC_STATE, tpmRegValidSts, 7, 1) 143 REG32(CRB_LOC_CTRL, 0x08) 144 REG32(CRB_LOC_STS, 0x0C) 145 FIELD(CRB_LOC_STS, Granted, 0, 1) 146 FIELD(CRB_LOC_STS, beenSeized, 1, 1) 147 REG32(CRB_INTF_ID, 0x30) 148 FIELD(CRB_INTF_ID, InterfaceType, 0, 4) 149 FIELD(CRB_INTF_ID, InterfaceVersion, 4, 4) 150 FIELD(CRB_INTF_ID, CapLocality, 8, 1) 151 FIELD(CRB_INTF_ID, CapCRBIdleBypass, 9, 1) 152 FIELD(CRB_INTF_ID, Reserved1, 10, 1) 153 FIELD(CRB_INTF_ID, CapDataXferSizeSupport, 11, 2) 154 FIELD(CRB_INTF_ID, CapFIFO, 13, 1) 155 FIELD(CRB_INTF_ID, CapCRB, 14, 1) 156 FIELD(CRB_INTF_ID, CapIFRes, 15, 2) 157 FIELD(CRB_INTF_ID, InterfaceSelector, 17, 2) 158 FIELD(CRB_INTF_ID, IntfSelLock, 19, 1) 159 FIELD(CRB_INTF_ID, Reserved2, 20, 4) 160 FIELD(CRB_INTF_ID, RID, 24, 8) 161 REG32(CRB_INTF_ID2, 0x34) 162 FIELD(CRB_INTF_ID2, VID, 0, 16) 163 FIELD(CRB_INTF_ID2, DID, 16, 16) 164 REG32(CRB_CTRL_EXT, 0x38) 165 REG32(CRB_CTRL_REQ, 0x40) 166 REG32(CRB_CTRL_STS, 0x44) 167 FIELD(CRB_CTRL_STS, tpmSts, 0, 1) 168 FIELD(CRB_CTRL_STS, tpmIdle, 1, 1) 169 REG32(CRB_CTRL_CANCEL, 0x48) 170 REG32(CRB_CTRL_START, 0x4C) 171 REG32(CRB_INT_ENABLED, 0x50) 172 REG32(CRB_INT_STS, 0x54) 173 REG32(CRB_CTRL_CMD_SIZE, 0x58) 174 REG32(CRB_CTRL_CMD_LADDR, 0x5C) 175 REG32(CRB_CTRL_CMD_HADDR, 0x60) 176 REG32(CRB_CTRL_RSP_SIZE, 0x64) 177 REG32(CRB_CTRL_RSP_ADDR, 0x68) 178 REG32(CRB_DATA_BUFFER, 0x80) 179 180 #define TPM_CRB_ADDR_BASE 0xFED40000 181 #define TPM_CRB_ADDR_SIZE 0x1000 182 #define TPM_CRB_ADDR_CTRL (TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ) 183 #define TPM_CRB_R_MAX R_CRB_DATA_BUFFER 184 185 #define TPM_LOG_AREA_MINIMUM_SIZE (64 * KiB) 186 187 #define TPM_TCPA_ACPI_CLASS_CLIENT 0 188 #define TPM_TCPA_ACPI_CLASS_SERVER 1 189 190 #define TPM2_ACPI_CLASS_CLIENT 0 191 #define TPM2_ACPI_CLASS_SERVER 1 192 193 #define TPM2_START_METHOD_MMIO 6 194 #define TPM2_START_METHOD_CRB 7 195 196 /* 197 * Physical Presence Interface 198 */ 199 #define TPM_PPI_ADDR_SIZE 0x400 200 #define TPM_PPI_ADDR_BASE 0xFED45000 201 202 #define TPM_PPI_VERSION_NONE 0 203 #define TPM_PPI_VERSION_1_30 1 204 205 /* whether function is blocked by BIOS settings; bits 0, 1, 2 */ 206 #define TPM_PPI_FUNC_NOT_IMPLEMENTED (0 << 0) 207 #define TPM_PPI_FUNC_BIOS_ONLY (1 << 0) 208 #define TPM_PPI_FUNC_BLOCKED (2 << 0) 209 #define TPM_PPI_FUNC_ALLOWED_USR_REQ (3 << 0) 210 #define TPM_PPI_FUNC_ALLOWED_USR_NOT_REQ (4 << 0) 211 #define TPM_PPI_FUNC_MASK (7 << 0) 212 213 /* TPM TIS I2C registers */ 214 #define TPM_I2C_REG_LOC_SEL 0x00 215 #define TPM_I2C_REG_ACCESS 0x04 216 #define TPM_I2C_REG_INT_ENABLE 0x08 217 #define TPM_I2C_REG_INT_CAPABILITY 0x14 218 #define TPM_I2C_REG_STS 0x18 219 #define TPM_I2C_REG_DATA_FIFO 0x24 220 #define TPM_I2C_REG_INTF_CAPABILITY 0x30 221 #define TPM_I2C_REG_I2C_DEV_ADDRESS 0x38 222 #define TPM_I2C_REG_DATA_CSUM_ENABLE 0x40 223 #define TPM_I2C_REG_DATA_CSUM_GET 0x44 224 #define TPM_I2C_REG_DID_VID 0x48 225 #define TPM_I2C_REG_RID 0x4c 226 #define TPM_I2C_REG_UNKNOWN 0xff 227 228 /* I2C specific interface capabilities */ 229 #define TPM_I2C_CAP_INTERFACE_TYPE (0x2 << 0) /* FIFO interface */ 230 #define TPM_I2C_CAP_INTERFACE_VER (0x0 << 4) /* TCG I2C intf 1.0 */ 231 #define TPM_I2C_CAP_TPM2_FAMILY (0x1 << 7) /* TPM 2.0 family. */ 232 #define TPM_I2C_CAP_DEV_ADDR_CHANGE (0x0 << 27) /* No dev addr chng */ 233 #define TPM_I2C_CAP_BURST_COUNT_STATIC (0x1 << 29) /* Burst count static */ 234 #define TPM_I2C_CAP_LOCALITY_CAP (0x1 << 25) /* 0-5 locality */ 235 #define TPM_I2C_CAP_BUS_SPEED (3 << 21) /* std and fast mode */ 236 237 /* 238 * TPM_I2C_STS masks for read/writing bits from/to TIS 239 * TPM_STS mask for read bits 31:26 must be zero 240 */ 241 #define TPM_I2C_STS_READ_MASK 0x00ffffdd 242 #define TPM_I2C_STS_WRITE_MASK 0x03000062 243 244 /* Checksum enabled. */ 245 #define TPM_DATA_CSUM_ENABLED 0x1 246 247 /* 248 * TPM_I2C_INT_ENABLE mask. Linux kernel does not support 249 * interrupts hence setting it to 0. 250 */ 251 #define TPM_I2C_INT_ENABLE_MASK 0x0 252 253 void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev); 254 255 #endif /* CONFIG_TPM */ 256 257 #endif /* HW_ACPI_TPM_H */ 258