1711b20b4SStefan Berger /* 2711b20b4SStefan Berger * tpm.h - TPM ACPI definitions 3711b20b4SStefan Berger * 4711b20b4SStefan Berger * Copyright (C) 2014 IBM Corporation 5711b20b4SStefan Berger * 6711b20b4SStefan Berger * Authors: 7711b20b4SStefan Berger * Stefan Berger <stefanb@us.ibm.com> 8711b20b4SStefan Berger * 9711b20b4SStefan Berger * This work is licensed under the terms of the GNU GPL, version 2 or later. 10711b20b4SStefan Berger * See the COPYING file in the top-level directory. 11711b20b4SStefan Berger * 12711b20b4SStefan Berger * Implementation of the TIS interface according to specs found at 13711b20b4SStefan Berger * http://www.trustedcomputinggroup.org 14711b20b4SStefan Berger * 15711b20b4SStefan Berger */ 16711b20b4SStefan Berger #ifndef HW_ACPI_TPM_H 17711b20b4SStefan Berger #define HW_ACPI_TPM_H 18711b20b4SStefan Berger 194ab6cb4cSMarc-André Lureau #include "hw/registerfields.h" 204ab6cb4cSMarc-André Lureau 21711b20b4SStefan Berger #define TPM_TIS_ADDR_BASE 0xFED40000 22711b20b4SStefan Berger #define TPM_TIS_ADDR_SIZE 0x5000 23711b20b4SStefan Berger 24711b20b4SStefan Berger #define TPM_TIS_IRQ 5 25711b20b4SStefan Berger 26*adb0e917SStefan Berger #define TPM_TIS_NUM_LOCALITIES 5 /* per spec */ 27*adb0e917SStefan Berger #define TPM_TIS_LOCALITY_SHIFT 12 28*adb0e917SStefan Berger 29*adb0e917SStefan Berger /* tis registers */ 30*adb0e917SStefan Berger #define TPM_TIS_REG_ACCESS 0x00 31*adb0e917SStefan Berger #define TPM_TIS_REG_INT_ENABLE 0x08 32*adb0e917SStefan Berger #define TPM_TIS_REG_INT_VECTOR 0x0c 33*adb0e917SStefan Berger #define TPM_TIS_REG_INT_STATUS 0x10 34*adb0e917SStefan Berger #define TPM_TIS_REG_INTF_CAPABILITY 0x14 35*adb0e917SStefan Berger #define TPM_TIS_REG_STS 0x18 36*adb0e917SStefan Berger #define TPM_TIS_REG_DATA_FIFO 0x24 37*adb0e917SStefan Berger #define TPM_TIS_REG_INTERFACE_ID 0x30 38*adb0e917SStefan Berger #define TPM_TIS_REG_DATA_XFIFO 0x80 39*adb0e917SStefan Berger #define TPM_TIS_REG_DATA_XFIFO_END 0xbc 40*adb0e917SStefan Berger #define TPM_TIS_REG_DID_VID 0xf00 41*adb0e917SStefan Berger #define TPM_TIS_REG_RID 0xf04 42*adb0e917SStefan Berger 43*adb0e917SStefan Berger /* vendor-specific registers */ 44*adb0e917SStefan Berger #define TPM_TIS_REG_DEBUG 0xf90 45*adb0e917SStefan Berger 46*adb0e917SStefan Berger #define TPM_TIS_STS_TPM_FAMILY_MASK (0x3 << 26)/* TPM 2.0 */ 47*adb0e917SStefan Berger #define TPM_TIS_STS_TPM_FAMILY1_2 (0 << 26) /* TPM 2.0 */ 48*adb0e917SStefan Berger #define TPM_TIS_STS_TPM_FAMILY2_0 (1 << 26) /* TPM 2.0 */ 49*adb0e917SStefan Berger #define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25) /* TPM 2.0 */ 50*adb0e917SStefan Berger #define TPM_TIS_STS_COMMAND_CANCEL (1 << 24) /* TPM 2.0 */ 51*adb0e917SStefan Berger 52*adb0e917SStefan Berger #define TPM_TIS_STS_VALID (1 << 7) 53*adb0e917SStefan Berger #define TPM_TIS_STS_COMMAND_READY (1 << 6) 54*adb0e917SStefan Berger #define TPM_TIS_STS_TPM_GO (1 << 5) 55*adb0e917SStefan Berger #define TPM_TIS_STS_DATA_AVAILABLE (1 << 4) 56*adb0e917SStefan Berger #define TPM_TIS_STS_EXPECT (1 << 3) 57*adb0e917SStefan Berger #define TPM_TIS_STS_SELFTEST_DONE (1 << 2) 58*adb0e917SStefan Berger #define TPM_TIS_STS_RESPONSE_RETRY (1 << 1) 59*adb0e917SStefan Berger 60*adb0e917SStefan Berger #define TPM_TIS_BURST_COUNT_SHIFT 8 61*adb0e917SStefan Berger #define TPM_TIS_BURST_COUNT(X) \ 62*adb0e917SStefan Berger ((X) << TPM_TIS_BURST_COUNT_SHIFT) 63*adb0e917SStefan Berger 64*adb0e917SStefan Berger #define TPM_TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) 65*adb0e917SStefan Berger #define TPM_TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) 66*adb0e917SStefan Berger #define TPM_TIS_ACCESS_BEEN_SEIZED (1 << 4) 67*adb0e917SStefan Berger #define TPM_TIS_ACCESS_SEIZE (1 << 3) 68*adb0e917SStefan Berger #define TPM_TIS_ACCESS_PENDING_REQUEST (1 << 2) 69*adb0e917SStefan Berger #define TPM_TIS_ACCESS_REQUEST_USE (1 << 1) 70*adb0e917SStefan Berger #define TPM_TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) 71*adb0e917SStefan Berger 72*adb0e917SStefan Berger #define TPM_TIS_INT_ENABLED (1 << 31) 73*adb0e917SStefan Berger #define TPM_TIS_INT_DATA_AVAILABLE (1 << 0) 74*adb0e917SStefan Berger #define TPM_TIS_INT_STS_VALID (1 << 1) 75*adb0e917SStefan Berger #define TPM_TIS_INT_LOCALITY_CHANGED (1 << 2) 76*adb0e917SStefan Berger #define TPM_TIS_INT_COMMAND_READY (1 << 7) 77*adb0e917SStefan Berger 78*adb0e917SStefan Berger #define TPM_TIS_INT_POLARITY_MASK (3 << 3) 79*adb0e917SStefan Berger #define TPM_TIS_INT_POLARITY_LOW_LEVEL (1 << 3) 80*adb0e917SStefan Berger 81*adb0e917SStefan Berger #define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \ 82*adb0e917SStefan Berger TPM_TIS_INT_DATA_AVAILABLE | \ 83*adb0e917SStefan Berger TPM_TIS_INT_STS_VALID | \ 84*adb0e917SStefan Berger TPM_TIS_INT_COMMAND_READY) 85*adb0e917SStefan Berger 86*adb0e917SStefan Berger #define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28) 87*adb0e917SStefan Berger #define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28) 88*adb0e917SStefan Berger #define TPM_TIS_CAP_DATA_TRANSFER_64B (3 << 9) 89*adb0e917SStefan Berger #define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9) 90*adb0e917SStefan Berger #define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8) 91*adb0e917SStefan Berger #define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL (1 << 4) /* support is mandatory */ 92*adb0e917SStefan Berger #define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \ 93*adb0e917SStefan Berger (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ 94*adb0e917SStefan Berger TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ 95*adb0e917SStefan Berger TPM_TIS_CAP_DATA_TRANSFER_64B | \ 96*adb0e917SStefan Berger TPM_TIS_CAP_INTERFACE_VERSION1_3 | \ 97*adb0e917SStefan Berger TPM_TIS_INTERRUPTS_SUPPORTED) 98*adb0e917SStefan Berger 99*adb0e917SStefan Berger #define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \ 100*adb0e917SStefan Berger (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ 101*adb0e917SStefan Berger TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ 102*adb0e917SStefan Berger TPM_TIS_CAP_DATA_TRANSFER_64B | \ 103*adb0e917SStefan Berger TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \ 104*adb0e917SStefan Berger TPM_TIS_INTERRUPTS_SUPPORTED) 105*adb0e917SStefan Berger 106*adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 (0xf) /* TPM 2.0 */ 107*adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_INTERFACE_FIFO (0x0) /* TPM 2.0 */ 108*adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4) /* TPM 2.0 */ 109*adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES (1 << 8) /* TPM 2.0 */ 110*adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED (1 << 13) /* TPM 2.0 */ 111*adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_INT_SEL_LOCK (1 << 19) /* TPM 2.0 */ 112*adb0e917SStefan Berger 113*adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \ 114*adb0e917SStefan Berger (TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \ 115*adb0e917SStefan Berger (~0u << 4)/* all of it is don't care */) 116*adb0e917SStefan Berger 117*adb0e917SStefan Berger /* if backend was a TPM 2.0: */ 118*adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \ 119*adb0e917SStefan Berger (TPM_TIS_IFACE_ID_INTERFACE_FIFO | \ 120*adb0e917SStefan Berger TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \ 121*adb0e917SStefan Berger TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \ 122*adb0e917SStefan Berger TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED) 123*adb0e917SStefan Berger 124*adb0e917SStefan Berger #define TPM_TIS_TPM_DID 0x0001 125*adb0e917SStefan Berger #define TPM_TIS_TPM_VID PCI_VENDOR_ID_IBM 126*adb0e917SStefan Berger #define TPM_TIS_TPM_RID 0x0001 127*adb0e917SStefan Berger 128*adb0e917SStefan Berger #define TPM_TIS_NO_DATA_BYTE 0xff 129*adb0e917SStefan Berger 130*adb0e917SStefan Berger 1314ab6cb4cSMarc-André Lureau REG32(CRB_LOC_STATE, 0x00) 1324ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STATE, tpmEstablished, 0, 1) 1334ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STATE, locAssigned, 1, 1) 1344ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STATE, activeLocality, 2, 3) 1354ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STATE, reserved, 5, 2) 1364ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STATE, tpmRegValidSts, 7, 1) 1374ab6cb4cSMarc-André Lureau REG32(CRB_LOC_CTRL, 0x08) 1384ab6cb4cSMarc-André Lureau REG32(CRB_LOC_STS, 0x0C) 1394ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STS, Granted, 0, 1) 1404ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STS, beenSeized, 1, 1) 1414ab6cb4cSMarc-André Lureau REG32(CRB_INTF_ID, 0x30) 1424ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, InterfaceType, 0, 4) 1434ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, InterfaceVersion, 4, 4) 1444ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, CapLocality, 8, 1) 1454ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, CapCRBIdleBypass, 9, 1) 1464ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, Reserved1, 10, 1) 1474ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, CapDataXferSizeSupport, 11, 2) 1484ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, CapFIFO, 13, 1) 1494ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, CapCRB, 14, 1) 1504ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, CapIFRes, 15, 2) 1514ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, InterfaceSelector, 17, 2) 1524ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, IntfSelLock, 19, 1) 1534ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, Reserved2, 20, 4) 1544ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, RID, 24, 8) 1554ab6cb4cSMarc-André Lureau REG32(CRB_INTF_ID2, 0x34) 1564ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID2, VID, 0, 16) 1574ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID2, DID, 16, 16) 1584ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_EXT, 0x38) 1594ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_REQ, 0x40) 1604ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_STS, 0x44) 1614ab6cb4cSMarc-André Lureau FIELD(CRB_CTRL_STS, tpmSts, 0, 1) 1624ab6cb4cSMarc-André Lureau FIELD(CRB_CTRL_STS, tpmIdle, 1, 1) 1634ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_CANCEL, 0x48) 1644ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_START, 0x4C) 1654ab6cb4cSMarc-André Lureau REG32(CRB_INT_ENABLED, 0x50) 1664ab6cb4cSMarc-André Lureau REG32(CRB_INT_STS, 0x54) 1674ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_CMD_SIZE, 0x58) 1684ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_CMD_LADDR, 0x5C) 1694ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_CMD_HADDR, 0x60) 1704ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_RSP_SIZE, 0x64) 1714ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_RSP_ADDR, 0x68) 1724ab6cb4cSMarc-André Lureau REG32(CRB_DATA_BUFFER, 0x80) 1734ab6cb4cSMarc-André Lureau 1744ab6cb4cSMarc-André Lureau #define TPM_CRB_ADDR_BASE 0xFED40000 1754ab6cb4cSMarc-André Lureau #define TPM_CRB_ADDR_SIZE 0x1000 1764ab6cb4cSMarc-André Lureau #define TPM_CRB_ADDR_CTRL (TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ) 1774ab6cb4cSMarc-André Lureau #define TPM_CRB_R_MAX R_CRB_DATA_BUFFER 1784ab6cb4cSMarc-André Lureau 179711b20b4SStefan Berger #define TPM_LOG_AREA_MINIMUM_SIZE (64 * 1024) 180711b20b4SStefan Berger 181711b20b4SStefan Berger #define TPM_TCPA_ACPI_CLASS_CLIENT 0 182711b20b4SStefan Berger #define TPM_TCPA_ACPI_CLASS_SERVER 1 183711b20b4SStefan Berger 1845cb18b3dSStefan Berger #define TPM2_ACPI_CLASS_CLIENT 0 1855cb18b3dSStefan Berger #define TPM2_ACPI_CLASS_SERVER 1 1865cb18b3dSStefan Berger 1875cb18b3dSStefan Berger #define TPM2_START_METHOD_MMIO 6 1884ab6cb4cSMarc-André Lureau #define TPM2_START_METHOD_CRB 7 1895cb18b3dSStefan Berger 190711b20b4SStefan Berger #endif /* HW_ACPI_TPM_H */ 191