1711b20b4SStefan Berger /* 2711b20b4SStefan Berger * tpm.h - TPM ACPI definitions 3711b20b4SStefan Berger * 4711b20b4SStefan Berger * Copyright (C) 2014 IBM Corporation 5711b20b4SStefan Berger * 6711b20b4SStefan Berger * Authors: 7711b20b4SStefan Berger * Stefan Berger <stefanb@us.ibm.com> 8711b20b4SStefan Berger * 9711b20b4SStefan Berger * This work is licensed under the terms of the GNU GPL, version 2 or later. 10711b20b4SStefan Berger * See the COPYING file in the top-level directory. 11711b20b4SStefan Berger * 12711b20b4SStefan Berger * Implementation of the TIS interface according to specs found at 13711b20b4SStefan Berger * http://www.trustedcomputinggroup.org 14711b20b4SStefan Berger * 15711b20b4SStefan Berger */ 16711b20b4SStefan Berger #ifndef HW_ACPI_TPM_H 17711b20b4SStefan Berger #define HW_ACPI_TPM_H 18711b20b4SStefan Berger 19*3d779b93SPhilippe Mathieu-Daudé #include "qemu/units.h" 204ab6cb4cSMarc-André Lureau #include "hw/registerfields.h" 214ab6cb4cSMarc-André Lureau 22711b20b4SStefan Berger #define TPM_TIS_ADDR_BASE 0xFED40000 23711b20b4SStefan Berger #define TPM_TIS_ADDR_SIZE 0x5000 24711b20b4SStefan Berger 25711b20b4SStefan Berger #define TPM_TIS_IRQ 5 26711b20b4SStefan Berger 27adb0e917SStefan Berger #define TPM_TIS_NUM_LOCALITIES 5 /* per spec */ 28adb0e917SStefan Berger #define TPM_TIS_LOCALITY_SHIFT 12 29adb0e917SStefan Berger 30adb0e917SStefan Berger /* tis registers */ 31adb0e917SStefan Berger #define TPM_TIS_REG_ACCESS 0x00 32adb0e917SStefan Berger #define TPM_TIS_REG_INT_ENABLE 0x08 33adb0e917SStefan Berger #define TPM_TIS_REG_INT_VECTOR 0x0c 34adb0e917SStefan Berger #define TPM_TIS_REG_INT_STATUS 0x10 35adb0e917SStefan Berger #define TPM_TIS_REG_INTF_CAPABILITY 0x14 36adb0e917SStefan Berger #define TPM_TIS_REG_STS 0x18 37adb0e917SStefan Berger #define TPM_TIS_REG_DATA_FIFO 0x24 38adb0e917SStefan Berger #define TPM_TIS_REG_INTERFACE_ID 0x30 39adb0e917SStefan Berger #define TPM_TIS_REG_DATA_XFIFO 0x80 40adb0e917SStefan Berger #define TPM_TIS_REG_DATA_XFIFO_END 0xbc 41adb0e917SStefan Berger #define TPM_TIS_REG_DID_VID 0xf00 42adb0e917SStefan Berger #define TPM_TIS_REG_RID 0xf04 43adb0e917SStefan Berger 44adb0e917SStefan Berger /* vendor-specific registers */ 45adb0e917SStefan Berger #define TPM_TIS_REG_DEBUG 0xf90 46adb0e917SStefan Berger 47adb0e917SStefan Berger #define TPM_TIS_STS_TPM_FAMILY_MASK (0x3 << 26)/* TPM 2.0 */ 48adb0e917SStefan Berger #define TPM_TIS_STS_TPM_FAMILY1_2 (0 << 26) /* TPM 2.0 */ 49adb0e917SStefan Berger #define TPM_TIS_STS_TPM_FAMILY2_0 (1 << 26) /* TPM 2.0 */ 50adb0e917SStefan Berger #define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25) /* TPM 2.0 */ 51adb0e917SStefan Berger #define TPM_TIS_STS_COMMAND_CANCEL (1 << 24) /* TPM 2.0 */ 52adb0e917SStefan Berger 53adb0e917SStefan Berger #define TPM_TIS_STS_VALID (1 << 7) 54adb0e917SStefan Berger #define TPM_TIS_STS_COMMAND_READY (1 << 6) 55adb0e917SStefan Berger #define TPM_TIS_STS_TPM_GO (1 << 5) 56adb0e917SStefan Berger #define TPM_TIS_STS_DATA_AVAILABLE (1 << 4) 57adb0e917SStefan Berger #define TPM_TIS_STS_EXPECT (1 << 3) 58adb0e917SStefan Berger #define TPM_TIS_STS_SELFTEST_DONE (1 << 2) 59adb0e917SStefan Berger #define TPM_TIS_STS_RESPONSE_RETRY (1 << 1) 60adb0e917SStefan Berger 61adb0e917SStefan Berger #define TPM_TIS_BURST_COUNT_SHIFT 8 62adb0e917SStefan Berger #define TPM_TIS_BURST_COUNT(X) \ 63adb0e917SStefan Berger ((X) << TPM_TIS_BURST_COUNT_SHIFT) 64adb0e917SStefan Berger 65adb0e917SStefan Berger #define TPM_TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) 66adb0e917SStefan Berger #define TPM_TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) 67adb0e917SStefan Berger #define TPM_TIS_ACCESS_BEEN_SEIZED (1 << 4) 68adb0e917SStefan Berger #define TPM_TIS_ACCESS_SEIZE (1 << 3) 69adb0e917SStefan Berger #define TPM_TIS_ACCESS_PENDING_REQUEST (1 << 2) 70adb0e917SStefan Berger #define TPM_TIS_ACCESS_REQUEST_USE (1 << 1) 71adb0e917SStefan Berger #define TPM_TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) 72adb0e917SStefan Berger 73adb0e917SStefan Berger #define TPM_TIS_INT_ENABLED (1 << 31) 74adb0e917SStefan Berger #define TPM_TIS_INT_DATA_AVAILABLE (1 << 0) 75adb0e917SStefan Berger #define TPM_TIS_INT_STS_VALID (1 << 1) 76adb0e917SStefan Berger #define TPM_TIS_INT_LOCALITY_CHANGED (1 << 2) 77adb0e917SStefan Berger #define TPM_TIS_INT_COMMAND_READY (1 << 7) 78adb0e917SStefan Berger 79adb0e917SStefan Berger #define TPM_TIS_INT_POLARITY_MASK (3 << 3) 80adb0e917SStefan Berger #define TPM_TIS_INT_POLARITY_LOW_LEVEL (1 << 3) 81adb0e917SStefan Berger 82adb0e917SStefan Berger #define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \ 83adb0e917SStefan Berger TPM_TIS_INT_DATA_AVAILABLE | \ 84adb0e917SStefan Berger TPM_TIS_INT_STS_VALID | \ 85adb0e917SStefan Berger TPM_TIS_INT_COMMAND_READY) 86adb0e917SStefan Berger 87adb0e917SStefan Berger #define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28) 88adb0e917SStefan Berger #define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28) 89adb0e917SStefan Berger #define TPM_TIS_CAP_DATA_TRANSFER_64B (3 << 9) 90adb0e917SStefan Berger #define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9) 91adb0e917SStefan Berger #define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8) 92adb0e917SStefan Berger #define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL (1 << 4) /* support is mandatory */ 93adb0e917SStefan Berger #define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \ 94adb0e917SStefan Berger (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ 95adb0e917SStefan Berger TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ 96adb0e917SStefan Berger TPM_TIS_CAP_DATA_TRANSFER_64B | \ 97adb0e917SStefan Berger TPM_TIS_CAP_INTERFACE_VERSION1_3 | \ 98adb0e917SStefan Berger TPM_TIS_INTERRUPTS_SUPPORTED) 99adb0e917SStefan Berger 100adb0e917SStefan Berger #define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \ 101adb0e917SStefan Berger (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ 102adb0e917SStefan Berger TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ 103adb0e917SStefan Berger TPM_TIS_CAP_DATA_TRANSFER_64B | \ 104adb0e917SStefan Berger TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \ 105adb0e917SStefan Berger TPM_TIS_INTERRUPTS_SUPPORTED) 106adb0e917SStefan Berger 107adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 (0xf) /* TPM 2.0 */ 108adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_INTERFACE_FIFO (0x0) /* TPM 2.0 */ 109adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4) /* TPM 2.0 */ 110adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES (1 << 8) /* TPM 2.0 */ 111adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED (1 << 13) /* TPM 2.0 */ 112adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_INT_SEL_LOCK (1 << 19) /* TPM 2.0 */ 113adb0e917SStefan Berger 114adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \ 115adb0e917SStefan Berger (TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \ 116adb0e917SStefan Berger (~0u << 4)/* all of it is don't care */) 117adb0e917SStefan Berger 118adb0e917SStefan Berger /* if backend was a TPM 2.0: */ 119adb0e917SStefan Berger #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \ 120adb0e917SStefan Berger (TPM_TIS_IFACE_ID_INTERFACE_FIFO | \ 121adb0e917SStefan Berger TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \ 122adb0e917SStefan Berger TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \ 123adb0e917SStefan Berger TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED) 124adb0e917SStefan Berger 125adb0e917SStefan Berger #define TPM_TIS_TPM_DID 0x0001 126adb0e917SStefan Berger #define TPM_TIS_TPM_VID PCI_VENDOR_ID_IBM 127adb0e917SStefan Berger #define TPM_TIS_TPM_RID 0x0001 128adb0e917SStefan Berger 129adb0e917SStefan Berger #define TPM_TIS_NO_DATA_BYTE 0xff 130adb0e917SStefan Berger 131adb0e917SStefan Berger 1324ab6cb4cSMarc-André Lureau REG32(CRB_LOC_STATE, 0x00) 1334ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STATE, tpmEstablished, 0, 1) 1344ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STATE, locAssigned, 1, 1) 1354ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STATE, activeLocality, 2, 3) 1364ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STATE, reserved, 5, 2) 1374ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STATE, tpmRegValidSts, 7, 1) 1384ab6cb4cSMarc-André Lureau REG32(CRB_LOC_CTRL, 0x08) 1394ab6cb4cSMarc-André Lureau REG32(CRB_LOC_STS, 0x0C) 1404ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STS, Granted, 0, 1) 1414ab6cb4cSMarc-André Lureau FIELD(CRB_LOC_STS, beenSeized, 1, 1) 1424ab6cb4cSMarc-André Lureau REG32(CRB_INTF_ID, 0x30) 1434ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, InterfaceType, 0, 4) 1444ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, InterfaceVersion, 4, 4) 1454ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, CapLocality, 8, 1) 1464ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, CapCRBIdleBypass, 9, 1) 1474ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, Reserved1, 10, 1) 1484ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, CapDataXferSizeSupport, 11, 2) 1494ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, CapFIFO, 13, 1) 1504ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, CapCRB, 14, 1) 1514ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, CapIFRes, 15, 2) 1524ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, InterfaceSelector, 17, 2) 1534ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, IntfSelLock, 19, 1) 1544ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, Reserved2, 20, 4) 1554ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID, RID, 24, 8) 1564ab6cb4cSMarc-André Lureau REG32(CRB_INTF_ID2, 0x34) 1574ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID2, VID, 0, 16) 1584ab6cb4cSMarc-André Lureau FIELD(CRB_INTF_ID2, DID, 16, 16) 1594ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_EXT, 0x38) 1604ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_REQ, 0x40) 1614ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_STS, 0x44) 1624ab6cb4cSMarc-André Lureau FIELD(CRB_CTRL_STS, tpmSts, 0, 1) 1634ab6cb4cSMarc-André Lureau FIELD(CRB_CTRL_STS, tpmIdle, 1, 1) 1644ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_CANCEL, 0x48) 1654ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_START, 0x4C) 1664ab6cb4cSMarc-André Lureau REG32(CRB_INT_ENABLED, 0x50) 1674ab6cb4cSMarc-André Lureau REG32(CRB_INT_STS, 0x54) 1684ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_CMD_SIZE, 0x58) 1694ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_CMD_LADDR, 0x5C) 1704ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_CMD_HADDR, 0x60) 1714ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_RSP_SIZE, 0x64) 1724ab6cb4cSMarc-André Lureau REG32(CRB_CTRL_RSP_ADDR, 0x68) 1734ab6cb4cSMarc-André Lureau REG32(CRB_DATA_BUFFER, 0x80) 1744ab6cb4cSMarc-André Lureau 1754ab6cb4cSMarc-André Lureau #define TPM_CRB_ADDR_BASE 0xFED40000 1764ab6cb4cSMarc-André Lureau #define TPM_CRB_ADDR_SIZE 0x1000 1774ab6cb4cSMarc-André Lureau #define TPM_CRB_ADDR_CTRL (TPM_CRB_ADDR_BASE + A_CRB_CTRL_REQ) 1784ab6cb4cSMarc-André Lureau #define TPM_CRB_R_MAX R_CRB_DATA_BUFFER 1794ab6cb4cSMarc-André Lureau 180*3d779b93SPhilippe Mathieu-Daudé #define TPM_LOG_AREA_MINIMUM_SIZE (64 * KiB) 181711b20b4SStefan Berger 182711b20b4SStefan Berger #define TPM_TCPA_ACPI_CLASS_CLIENT 0 183711b20b4SStefan Berger #define TPM_TCPA_ACPI_CLASS_SERVER 1 184711b20b4SStefan Berger 1855cb18b3dSStefan Berger #define TPM2_ACPI_CLASS_CLIENT 0 1865cb18b3dSStefan Berger #define TPM2_ACPI_CLASS_SERVER 1 1875cb18b3dSStefan Berger 1885cb18b3dSStefan Berger #define TPM2_START_METHOD_MMIO 6 1894ab6cb4cSMarc-André Lureau #define TPM2_START_METHOD_CRB 7 1905cb18b3dSStefan Berger 191711b20b4SStefan Berger #endif /* HW_ACPI_TPM_H */ 192