1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License as published by 4 * the Free Software Foundation; either version 2 of the License, or 5 * (at your option) any later version. 6 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 12 * You should have received a copy of the GNU General Public License along 13 * with this program; if not, see <http://www.gnu.org/licenses/>. 14 */ 15 #ifndef QEMU_ACPI_DEFS_H 16 #define QEMU_ACPI_DEFS_H 17 18 enum { 19 ACPI_FADT_F_WBINVD, 20 ACPI_FADT_F_WBINVD_FLUSH, 21 ACPI_FADT_F_PROC_C1, 22 ACPI_FADT_F_P_LVL2_UP, 23 ACPI_FADT_F_PWR_BUTTON, 24 ACPI_FADT_F_SLP_BUTTON, 25 ACPI_FADT_F_FIX_RTC, 26 ACPI_FADT_F_RTC_S4, 27 ACPI_FADT_F_TMR_VAL_EXT, 28 ACPI_FADT_F_DCK_CAP, 29 ACPI_FADT_F_RESET_REG_SUP, 30 ACPI_FADT_F_SEALED_CASE, 31 ACPI_FADT_F_HEADLESS, 32 ACPI_FADT_F_CPU_SW_SLP, 33 ACPI_FADT_F_PCI_EXP_WAK, 34 ACPI_FADT_F_USE_PLATFORM_CLOCK, 35 ACPI_FADT_F_S4_RTC_STS_VALID, 36 ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE, 37 ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL, 38 ACPI_FADT_F_FORCE_APIC_PHYSICAL_DESTINATION_MODE, 39 ACPI_FADT_F_HW_REDUCED_ACPI, 40 ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE, 41 }; 42 43 /* 44 * ACPI 2.0 Generic Address Space definition. 45 */ 46 struct Acpi20GenericAddress { 47 uint8_t address_space_id; 48 uint8_t register_bit_width; 49 uint8_t register_bit_offset; 50 uint8_t reserved; 51 uint64_t address; 52 } QEMU_PACKED; 53 typedef struct Acpi20GenericAddress Acpi20GenericAddress; 54 55 struct AcpiRsdpDescriptor { /* Root System Descriptor Pointer */ 56 uint64_t signature; /* ACPI signature, contains "RSD PTR " */ 57 uint8_t checksum; /* To make sum of struct == 0 */ 58 uint8_t oem_id [6]; /* OEM identification */ 59 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */ 60 uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */ 61 uint32_t length; /* XSDT Length in bytes including hdr */ 62 uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */ 63 uint8_t extended_checksum; /* Checksum of entire table */ 64 uint8_t reserved [3]; /* Reserved field must be 0 */ 65 } QEMU_PACKED; 66 typedef struct AcpiRsdpDescriptor AcpiRsdpDescriptor; 67 68 /* Table structure from Linux kernel (the ACPI tables are under the 69 BSD license) */ 70 71 72 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \ 73 uint32_t signature; /* ACPI signature (4 ASCII characters) */ \ 74 uint32_t length; /* Length of table, in bytes, including header */ \ 75 uint8_t revision; /* ACPI Specification minor version # */ \ 76 uint8_t checksum; /* To make sum of entire table == 0 */ \ 77 uint8_t oem_id [6]; /* OEM identification */ \ 78 uint8_t oem_table_id [8]; /* OEM table identification */ \ 79 uint32_t oem_revision; /* OEM revision number */ \ 80 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */ \ 81 uint32_t asl_compiler_revision; /* ASL compiler revision number */ 82 83 84 struct AcpiTableHeader /* ACPI common table header */ 85 { 86 ACPI_TABLE_HEADER_DEF 87 } QEMU_PACKED; 88 typedef struct AcpiTableHeader AcpiTableHeader; 89 90 /* 91 * ACPI Fixed ACPI Description Table (FADT) 92 */ 93 #define ACPI_FADT_COMMON_DEF /* FADT common definition */ \ 94 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \ 95 uint32_t firmware_ctrl; /* Physical address of FACS */ \ 96 uint32_t dsdt; /* Physical address of DSDT */ \ 97 uint8_t model; /* System Interrupt Model */ \ 98 uint8_t reserved1; /* Reserved */ \ 99 uint16_t sci_int; /* System vector of SCI interrupt */ \ 100 uint32_t smi_cmd; /* Port address of SMI command port */ \ 101 uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ \ 102 uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ \ 103 /* Value to write to SMI CMD to enter S4BIOS state */ \ 104 uint8_t S4bios_req; \ 105 uint8_t reserved2; /* Reserved - must be zero */ \ 106 /* Port address of Power Mgt 1a acpi_event Reg Blk */ \ 107 uint32_t pm1a_evt_blk; \ 108 /* Port address of Power Mgt 1b acpi_event Reg Blk */ \ 109 uint32_t pm1b_evt_blk; \ 110 uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ \ 111 uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ \ 112 uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ \ 113 uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \ 114 /* Port addr of General Purpose acpi_event 0 Reg Blk */ \ 115 uint32_t gpe0_blk; \ 116 /* Port addr of General Purpose acpi_event 1 Reg Blk */ \ 117 uint32_t gpe1_blk; \ 118 uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ \ 119 uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ \ 120 uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ \ 121 uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ \ 122 uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ \ 123 uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ \ 124 uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ \ 125 uint8_t reserved3; /* Reserved */ \ 126 uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ \ 127 uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ \ 128 uint16_t flush_size; /* Size of area read to flush caches */ \ 129 uint16_t flush_stride; /* Stride used in flushing caches */ \ 130 uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ \ 131 uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ \ 132 uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \ 133 uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \ 134 uint8_t century; /* Index to century in RTC CMOS RAM */ \ 135 /* IA-PC Boot Architecture Flags (see below for individual flags) */ \ 136 uint16_t boot_flags; \ 137 uint8_t reserved; /* Reserved, must be zero */ \ 138 /* Miscellaneous flag bits (see below for individual flags) */ \ 139 uint32_t flags; \ 140 /* 64-bit address of the Reset register */ \ 141 struct AcpiGenericAddress reset_register; \ 142 /* Value to write to the reset_register port to reset the system */ \ 143 uint8_t reset_value; \ 144 /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */ \ 145 uint16_t arm_boot_flags; \ 146 uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */ \ 147 uint64_t Xfacs; /* 64-bit physical address of FACS */ \ 148 uint64_t Xdsdt; /* 64-bit physical address of DSDT */ \ 149 /* 64-bit Extended Power Mgt 1a Event Reg Blk address */ \ 150 struct AcpiGenericAddress xpm1a_event_block; \ 151 /* 64-bit Extended Power Mgt 1b Event Reg Blk address */ \ 152 struct AcpiGenericAddress xpm1b_event_block; \ 153 /* 64-bit Extended Power Mgt 1a Control Reg Blk address */ \ 154 struct AcpiGenericAddress xpm1a_control_block; \ 155 /* 64-bit Extended Power Mgt 1b Control Reg Blk address */ \ 156 struct AcpiGenericAddress xpm1b_control_block; \ 157 /* 64-bit Extended Power Mgt 2 Control Reg Blk address */ \ 158 struct AcpiGenericAddress xpm2_control_block; \ 159 /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */ \ 160 struct AcpiGenericAddress xpm_timer_block; \ 161 /* 64-bit Extended General Purpose Event 0 Reg Blk address */ \ 162 struct AcpiGenericAddress xgpe0_block; \ 163 /* 64-bit Extended General Purpose Event 1 Reg Blk address */ \ 164 struct AcpiGenericAddress xgpe1_block; \ 165 166 struct AcpiGenericAddress { 167 uint8_t space_id; /* Address space where struct or register exists */ 168 uint8_t bit_width; /* Size in bits of given register */ 169 uint8_t bit_offset; /* Bit offset within the register */ 170 uint8_t access_width; /* Minimum Access size (ACPI 3.0) */ 171 uint64_t address; /* 64-bit address of struct or register */ 172 } QEMU_PACKED; 173 174 struct AcpiFadtDescriptorRev3 { 175 ACPI_FADT_COMMON_DEF 176 } QEMU_PACKED; 177 typedef struct AcpiFadtDescriptorRev3 AcpiFadtDescriptorRev3; 178 179 struct AcpiFadtDescriptorRev5_1 { 180 ACPI_FADT_COMMON_DEF 181 /* 64-bit Sleep Control register (ACPI 5.0) */ 182 struct AcpiGenericAddress sleep_control; 183 /* 64-bit Sleep Status register (ACPI 5.0) */ 184 struct AcpiGenericAddress sleep_status; 185 } QEMU_PACKED; 186 187 typedef struct AcpiFadtDescriptorRev5_1 AcpiFadtDescriptorRev5_1; 188 189 #define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0) 190 #define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1) 191 192 /* 193 * Serial Port Console Redirection Table (SPCR), Rev. 1.02 194 * 195 * For .interface_type see Debug Port Table 2 (DBG2) serial port 196 * subtypes in Table 3, Rev. May 22, 2012 197 */ 198 struct AcpiSerialPortConsoleRedirection { 199 ACPI_TABLE_HEADER_DEF 200 uint8_t interface_type; 201 uint8_t reserved1[3]; 202 struct AcpiGenericAddress base_address; 203 uint8_t interrupt_types; 204 uint8_t irq; 205 uint32_t gsi; 206 uint8_t baud; 207 uint8_t parity; 208 uint8_t stopbits; 209 uint8_t flowctrl; 210 uint8_t term_type; 211 uint8_t reserved2; 212 uint16_t pci_device_id; 213 uint16_t pci_vendor_id; 214 uint8_t pci_bus; 215 uint8_t pci_slot; 216 uint8_t pci_func; 217 uint32_t pci_flags; 218 uint8_t pci_seg; 219 uint32_t reserved3; 220 } QEMU_PACKED; 221 typedef struct AcpiSerialPortConsoleRedirection 222 AcpiSerialPortConsoleRedirection; 223 224 /* 225 * ACPI 1.0 Root System Description Table (RSDT) 226 */ 227 struct AcpiRsdtDescriptorRev1 228 { 229 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 230 uint32_t table_offset_entry[0]; /* Array of pointers to other */ 231 /* ACPI tables */ 232 } QEMU_PACKED; 233 typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1; 234 235 /* 236 * ACPI 1.0 Firmware ACPI Control Structure (FACS) 237 */ 238 struct AcpiFacsDescriptorRev1 239 { 240 uint32_t signature; /* ACPI Signature */ 241 uint32_t length; /* Length of structure, in bytes */ 242 uint32_t hardware_signature; /* Hardware configuration signature */ 243 uint32_t firmware_waking_vector; /* ACPI OS waking vector */ 244 uint32_t global_lock; /* Global Lock */ 245 uint32_t flags; 246 uint8_t resverved3 [40]; /* Reserved - must be zero */ 247 } QEMU_PACKED; 248 typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1; 249 250 /* 251 * Differentiated System Description Table (DSDT) 252 */ 253 254 /* 255 * MADT values and structures 256 */ 257 258 /* Values for MADT PCATCompat */ 259 260 #define ACPI_DUAL_PIC 0 261 #define ACPI_MULTIPLE_APIC 1 262 263 /* Master MADT */ 264 265 struct AcpiMultipleApicTable 266 { 267 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 268 uint32_t local_apic_address; /* Physical address of local APIC */ 269 uint32_t flags; 270 } QEMU_PACKED; 271 typedef struct AcpiMultipleApicTable AcpiMultipleApicTable; 272 273 /* Values for Type in APIC sub-headers */ 274 275 #define ACPI_APIC_PROCESSOR 0 276 #define ACPI_APIC_IO 1 277 #define ACPI_APIC_XRUPT_OVERRIDE 2 278 #define ACPI_APIC_NMI 3 279 #define ACPI_APIC_LOCAL_NMI 4 280 #define ACPI_APIC_ADDRESS_OVERRIDE 5 281 #define ACPI_APIC_IO_SAPIC 6 282 #define ACPI_APIC_LOCAL_SAPIC 7 283 #define ACPI_APIC_XRUPT_SOURCE 8 284 #define ACPI_APIC_LOCAL_X2APIC 9 285 #define ACPI_APIC_LOCAL_X2APIC_NMI 10 286 #define ACPI_APIC_GENERIC_CPU_INTERFACE 11 287 #define ACPI_APIC_GENERIC_DISTRIBUTOR 12 288 #define ACPI_APIC_GENERIC_MSI_FRAME 13 289 #define ACPI_APIC_GENERIC_REDISTRIBUTOR 14 290 #define ACPI_APIC_GENERIC_TRANSLATOR 15 291 #define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */ 292 293 /* 294 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) 295 */ 296 #define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\ 297 uint8_t type; \ 298 uint8_t length; 299 300 /* Sub-structures for MADT */ 301 302 struct AcpiMadtProcessorApic 303 { 304 ACPI_SUB_HEADER_DEF 305 uint8_t processor_id; /* ACPI processor id */ 306 uint8_t local_apic_id; /* Processor's local APIC id */ 307 uint32_t flags; 308 } QEMU_PACKED; 309 typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic; 310 311 struct AcpiMadtIoApic 312 { 313 ACPI_SUB_HEADER_DEF 314 uint8_t io_apic_id; /* I/O APIC ID */ 315 uint8_t reserved; /* Reserved - must be zero */ 316 uint32_t address; /* APIC physical address */ 317 uint32_t interrupt; /* Global system interrupt where INTI 318 * lines start */ 319 } QEMU_PACKED; 320 typedef struct AcpiMadtIoApic AcpiMadtIoApic; 321 322 struct AcpiMadtIntsrcovr { 323 ACPI_SUB_HEADER_DEF 324 uint8_t bus; 325 uint8_t source; 326 uint32_t gsi; 327 uint16_t flags; 328 } QEMU_PACKED; 329 typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr; 330 331 struct AcpiMadtLocalNmi { 332 ACPI_SUB_HEADER_DEF 333 uint8_t processor_id; /* ACPI processor id */ 334 uint16_t flags; /* MPS INTI flags */ 335 uint8_t lint; /* Local APIC LINT# */ 336 } QEMU_PACKED; 337 typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi; 338 339 struct AcpiMadtProcessorX2Apic { 340 ACPI_SUB_HEADER_DEF 341 uint16_t reserved; 342 uint32_t x2apic_id; /* Processor's local x2APIC ID */ 343 uint32_t flags; 344 uint32_t uid; /* Processor object _UID */ 345 } QEMU_PACKED; 346 typedef struct AcpiMadtProcessorX2Apic AcpiMadtProcessorX2Apic; 347 348 struct AcpiMadtLocalX2ApicNmi { 349 ACPI_SUB_HEADER_DEF 350 uint16_t flags; /* MPS INTI flags */ 351 uint32_t uid; /* Processor object _UID */ 352 uint8_t lint; /* Local APIC LINT# */ 353 uint8_t reserved[3]; /* Local APIC LINT# */ 354 } QEMU_PACKED; 355 typedef struct AcpiMadtLocalX2ApicNmi AcpiMadtLocalX2ApicNmi; 356 357 struct AcpiMadtGenericCpuInterface { 358 ACPI_SUB_HEADER_DEF 359 uint16_t reserved; 360 uint32_t cpu_interface_number; 361 uint32_t uid; 362 uint32_t flags; 363 uint32_t parking_version; 364 uint32_t performance_interrupt; 365 uint64_t parked_address; 366 uint64_t base_address; 367 uint64_t gicv_base_address; 368 uint64_t gich_base_address; 369 uint32_t vgic_interrupt; 370 uint64_t gicr_base_address; 371 uint64_t arm_mpidr; 372 } QEMU_PACKED; 373 374 typedef struct AcpiMadtGenericCpuInterface AcpiMadtGenericCpuInterface; 375 376 /* GICC CPU Interface Flags */ 377 #define ACPI_MADT_GICC_ENABLED 1 378 379 struct AcpiMadtGenericDistributor { 380 ACPI_SUB_HEADER_DEF 381 uint16_t reserved; 382 uint32_t gic_id; 383 uint64_t base_address; 384 uint32_t global_irq_base; 385 /* ACPI 5.1 Errata 1228 Present GIC version in MADT table */ 386 uint8_t version; 387 uint8_t reserved2[3]; 388 } QEMU_PACKED; 389 390 typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor; 391 392 struct AcpiMadtGenericMsiFrame { 393 ACPI_SUB_HEADER_DEF 394 uint16_t reserved; 395 uint32_t gic_msi_frame_id; 396 uint64_t base_address; 397 uint32_t flags; 398 uint16_t spi_count; 399 uint16_t spi_base; 400 } QEMU_PACKED; 401 402 typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame; 403 404 struct AcpiMadtGenericRedistributor { 405 ACPI_SUB_HEADER_DEF 406 uint16_t reserved; 407 uint64_t base_address; 408 uint32_t range_length; 409 } QEMU_PACKED; 410 411 typedef struct AcpiMadtGenericRedistributor AcpiMadtGenericRedistributor; 412 413 struct AcpiMadtGenericTranslator { 414 ACPI_SUB_HEADER_DEF 415 uint16_t reserved; 416 uint32_t translation_id; 417 uint64_t base_address; 418 uint32_t reserved2; 419 } QEMU_PACKED; 420 421 typedef struct AcpiMadtGenericTranslator AcpiMadtGenericTranslator; 422 423 /* 424 * Generic Timer Description Table (GTDT) 425 */ 426 #define ACPI_GTDT_INTERRUPT_MODE_LEVEL (0 << 0) 427 #define ACPI_GTDT_INTERRUPT_MODE_EDGE (1 << 0) 428 #define ACPI_GTDT_CAP_ALWAYS_ON (1 << 2) 429 430 struct AcpiGenericTimerTable { 431 ACPI_TABLE_HEADER_DEF 432 uint64_t counter_block_addresss; 433 uint32_t reserved; 434 uint32_t secure_el1_interrupt; 435 uint32_t secure_el1_flags; 436 uint32_t non_secure_el1_interrupt; 437 uint32_t non_secure_el1_flags; 438 uint32_t virtual_timer_interrupt; 439 uint32_t virtual_timer_flags; 440 uint32_t non_secure_el2_interrupt; 441 uint32_t non_secure_el2_flags; 442 uint64_t counter_read_block_address; 443 uint32_t platform_timer_count; 444 uint32_t platform_timer_offset; 445 } QEMU_PACKED; 446 typedef struct AcpiGenericTimerTable AcpiGenericTimerTable; 447 448 /* 449 * HPET Description Table 450 */ 451 struct Acpi20Hpet { 452 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 453 uint32_t timer_block_id; 454 Acpi20GenericAddress addr; 455 uint8_t hpet_number; 456 uint16_t min_tick; 457 uint8_t page_protect; 458 } QEMU_PACKED; 459 typedef struct Acpi20Hpet Acpi20Hpet; 460 461 /* 462 * SRAT (NUMA topology description) table 463 */ 464 465 struct AcpiSystemResourceAffinityTable 466 { 467 ACPI_TABLE_HEADER_DEF 468 uint32_t reserved1; 469 uint32_t reserved2[2]; 470 } QEMU_PACKED; 471 typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable; 472 473 #define ACPI_SRAT_PROCESSOR_APIC 0 474 #define ACPI_SRAT_MEMORY 1 475 #define ACPI_SRAT_PROCESSOR_x2APIC 2 476 #define ACPI_SRAT_PROCESSOR_GICC 3 477 478 struct AcpiSratProcessorAffinity 479 { 480 ACPI_SUB_HEADER_DEF 481 uint8_t proximity_lo; 482 uint8_t local_apic_id; 483 uint32_t flags; 484 uint8_t local_sapic_eid; 485 uint8_t proximity_hi[3]; 486 uint32_t reserved; 487 } QEMU_PACKED; 488 typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity; 489 490 struct AcpiSratProcessorX2ApicAffinity { 491 ACPI_SUB_HEADER_DEF 492 uint16_t reserved; 493 uint32_t proximity_domain; 494 uint32_t x2apic_id; 495 uint32_t flags; 496 uint32_t clk_domain; 497 uint32_t reserved2; 498 } QEMU_PACKED; 499 typedef struct AcpiSratProcessorX2ApicAffinity AcpiSratProcessorX2ApicAffinity; 500 501 struct AcpiSratMemoryAffinity 502 { 503 ACPI_SUB_HEADER_DEF 504 uint32_t proximity; 505 uint16_t reserved1; 506 uint64_t base_addr; 507 uint64_t range_length; 508 uint32_t reserved2; 509 uint32_t flags; 510 uint32_t reserved3[2]; 511 } QEMU_PACKED; 512 typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity; 513 514 struct AcpiSratProcessorGiccAffinity 515 { 516 ACPI_SUB_HEADER_DEF 517 uint32_t proximity; 518 uint32_t acpi_processor_uid; 519 uint32_t flags; 520 uint32_t clock_domain; 521 } QEMU_PACKED; 522 523 typedef struct AcpiSratProcessorGiccAffinity AcpiSratProcessorGiccAffinity; 524 525 /* PCI fw r3.0 MCFG table. */ 526 /* Subtable */ 527 struct AcpiMcfgAllocation { 528 uint64_t address; /* Base address, processor-relative */ 529 uint16_t pci_segment; /* PCI segment group number */ 530 uint8_t start_bus_number; /* Starting PCI Bus number */ 531 uint8_t end_bus_number; /* Final PCI Bus number */ 532 uint32_t reserved; 533 } QEMU_PACKED; 534 typedef struct AcpiMcfgAllocation AcpiMcfgAllocation; 535 536 struct AcpiTableMcfg { 537 ACPI_TABLE_HEADER_DEF; 538 uint8_t reserved[8]; 539 AcpiMcfgAllocation allocation[0]; 540 } QEMU_PACKED; 541 typedef struct AcpiTableMcfg AcpiTableMcfg; 542 543 /* 544 * TCPA Description Table 545 * 546 * Following Level 00, Rev 00.37 of specs: 547 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 548 */ 549 struct Acpi20Tcpa { 550 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 551 uint16_t platform_class; 552 uint32_t log_area_minimum_length; 553 uint64_t log_area_start_address; 554 } QEMU_PACKED; 555 typedef struct Acpi20Tcpa Acpi20Tcpa; 556 557 /* 558 * TPM2 559 * 560 * Following Level 00, Rev 00.37 of specs: 561 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 562 */ 563 struct Acpi20TPM2 { 564 ACPI_TABLE_HEADER_DEF 565 uint16_t platform_class; 566 uint16_t reserved; 567 uint64_t control_area_address; 568 uint32_t start_method; 569 } QEMU_PACKED; 570 typedef struct Acpi20TPM2 Acpi20TPM2; 571 572 /* DMAR - DMA Remapping table r2.2 */ 573 struct AcpiTableDmar { 574 ACPI_TABLE_HEADER_DEF 575 uint8_t host_address_width; /* Maximum DMA physical addressability */ 576 uint8_t flags; 577 uint8_t reserved[10]; 578 } QEMU_PACKED; 579 typedef struct AcpiTableDmar AcpiTableDmar; 580 581 /* Masks for Flags field above */ 582 #define ACPI_DMAR_INTR_REMAP 1 583 #define ACPI_DMAR_X2APIC_OPT_OUT (1 << 1) 584 585 /* Values for sub-structure type for DMAR */ 586 enum { 587 ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, /* DRHD */ 588 ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, /* RMRR */ 589 ACPI_DMAR_TYPE_ATSR = 2, /* ATSR */ 590 ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, /* RHSR */ 591 ACPI_DMAR_TYPE_ANDD = 4, /* ANDD */ 592 ACPI_DMAR_TYPE_RESERVED = 5 /* Reserved for furture use */ 593 }; 594 595 /* 596 * Sub-structures for DMAR 597 */ 598 599 /* Device scope structure for DRHD. */ 600 struct AcpiDmarDeviceScope { 601 uint8_t entry_type; 602 uint8_t length; 603 uint16_t reserved; 604 uint8_t enumeration_id; 605 uint8_t bus; 606 struct { 607 uint8_t device; 608 uint8_t function; 609 } path[0]; 610 } QEMU_PACKED; 611 typedef struct AcpiDmarDeviceScope AcpiDmarDeviceScope; 612 613 /* Type 0: Hardware Unit Definition */ 614 struct AcpiDmarHardwareUnit { 615 uint16_t type; 616 uint16_t length; 617 uint8_t flags; 618 uint8_t reserved; 619 uint16_t pci_segment; /* The PCI Segment associated with this unit */ 620 uint64_t address; /* Base address of remapping hardware register-set */ 621 AcpiDmarDeviceScope scope[0]; 622 } QEMU_PACKED; 623 typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit; 624 625 /* Type 2: Root Port ATS Capability Reporting Structure */ 626 struct AcpiDmarRootPortATS { 627 uint16_t type; 628 uint16_t length; 629 uint8_t flags; 630 uint8_t reserved; 631 uint16_t pci_segment; 632 AcpiDmarDeviceScope scope[0]; 633 } QEMU_PACKED; 634 typedef struct AcpiDmarRootPortATS AcpiDmarRootPortATS; 635 636 /* Masks for Flags field above */ 637 #define ACPI_DMAR_INCLUDE_PCI_ALL 1 638 #define ACPI_DMAR_ATSR_ALL_PORTS 1 639 640 /* 641 * Input Output Remapping Table (IORT) 642 * Conforms to "IO Remapping Table System Software on ARM Platforms", 643 * Document number: ARM DEN 0049B, October 2015 644 */ 645 646 struct AcpiIortTable { 647 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 648 uint32_t node_count; 649 uint32_t node_offset; 650 uint32_t reserved; 651 } QEMU_PACKED; 652 typedef struct AcpiIortTable AcpiIortTable; 653 654 /* 655 * IORT node types 656 */ 657 658 #define ACPI_IORT_NODE_HEADER_DEF /* Node format common fields */ \ 659 uint8_t type; \ 660 uint16_t length; \ 661 uint8_t revision; \ 662 uint32_t reserved; \ 663 uint32_t mapping_count; \ 664 uint32_t mapping_offset; 665 666 /* Values for node Type above */ 667 enum { 668 ACPI_IORT_NODE_ITS_GROUP = 0x00, 669 ACPI_IORT_NODE_NAMED_COMPONENT = 0x01, 670 ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02, 671 ACPI_IORT_NODE_SMMU = 0x03, 672 ACPI_IORT_NODE_SMMU_V3 = 0x04 673 }; 674 675 struct AcpiIortIdMapping { 676 uint32_t input_base; 677 uint32_t id_count; 678 uint32_t output_base; 679 uint32_t output_reference; 680 uint32_t flags; 681 } QEMU_PACKED; 682 typedef struct AcpiIortIdMapping AcpiIortIdMapping; 683 684 struct AcpiIortMemoryAccess { 685 uint32_t cache_coherency; 686 uint8_t hints; 687 uint16_t reserved; 688 uint8_t memory_flags; 689 } QEMU_PACKED; 690 typedef struct AcpiIortMemoryAccess AcpiIortMemoryAccess; 691 692 struct AcpiIortItsGroup { 693 ACPI_IORT_NODE_HEADER_DEF 694 uint32_t its_count; 695 uint32_t identifiers[0]; 696 } QEMU_PACKED; 697 typedef struct AcpiIortItsGroup AcpiIortItsGroup; 698 699 struct AcpiIortRC { 700 ACPI_IORT_NODE_HEADER_DEF 701 AcpiIortMemoryAccess memory_properties; 702 uint32_t ats_attribute; 703 uint32_t pci_segment_number; 704 AcpiIortIdMapping id_mapping_array[0]; 705 } QEMU_PACKED; 706 typedef struct AcpiIortRC AcpiIortRC; 707 708 #endif 709