1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License as published by 4 * the Free Software Foundation; either version 2 of the License, or 5 * (at your option) any later version. 6 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 12 * You should have received a copy of the GNU General Public License along 13 * with this program; if not, see <http://www.gnu.org/licenses/>. 14 */ 15 #ifndef QEMU_ACPI_DEFS_H 16 #define QEMU_ACPI_DEFS_H 17 18 enum { 19 ACPI_FADT_F_WBINVD, 20 ACPI_FADT_F_WBINVD_FLUSH, 21 ACPI_FADT_F_PROC_C1, 22 ACPI_FADT_F_P_LVL2_UP, 23 ACPI_FADT_F_PWR_BUTTON, 24 ACPI_FADT_F_SLP_BUTTON, 25 ACPI_FADT_F_FIX_RTC, 26 ACPI_FADT_F_RTC_S4, 27 ACPI_FADT_F_TMR_VAL_EXT, 28 ACPI_FADT_F_DCK_CAP, 29 ACPI_FADT_F_RESET_REG_SUP, 30 ACPI_FADT_F_SEALED_CASE, 31 ACPI_FADT_F_HEADLESS, 32 ACPI_FADT_F_CPU_SW_SLP, 33 ACPI_FADT_F_PCI_EXP_WAK, 34 ACPI_FADT_F_USE_PLATFORM_CLOCK, 35 ACPI_FADT_F_S4_RTC_STS_VALID, 36 ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE, 37 ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL, 38 ACPI_FADT_F_FORCE_APIC_PHYSICAL_DESTINATION_MODE, 39 ACPI_FADT_F_HW_REDUCED_ACPI, 40 ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE, 41 }; 42 43 /* 44 * ACPI 2.0 Generic Address Space definition. 45 */ 46 struct Acpi20GenericAddress { 47 uint8_t address_space_id; 48 uint8_t register_bit_width; 49 uint8_t register_bit_offset; 50 uint8_t reserved; 51 uint64_t address; 52 } QEMU_PACKED; 53 typedef struct Acpi20GenericAddress Acpi20GenericAddress; 54 55 struct AcpiRsdpDescriptor { /* Root System Descriptor Pointer */ 56 uint64_t signature; /* ACPI signature, contains "RSD PTR " */ 57 uint8_t checksum; /* To make sum of struct == 0 */ 58 uint8_t oem_id [6]; /* OEM identification */ 59 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */ 60 uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */ 61 uint32_t length; /* XSDT Length in bytes including hdr */ 62 uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */ 63 uint8_t extended_checksum; /* Checksum of entire table */ 64 uint8_t reserved [3]; /* Reserved field must be 0 */ 65 } QEMU_PACKED; 66 typedef struct AcpiRsdpDescriptor AcpiRsdpDescriptor; 67 68 /* Table structure from Linux kernel (the ACPI tables are under the 69 BSD license) */ 70 71 72 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \ 73 uint32_t signature; /* ACPI signature (4 ASCII characters) */ \ 74 uint32_t length; /* Length of table, in bytes, including header */ \ 75 uint8_t revision; /* ACPI Specification minor version # */ \ 76 uint8_t checksum; /* To make sum of entire table == 0 */ \ 77 uint8_t oem_id [6]; /* OEM identification */ \ 78 uint8_t oem_table_id [8]; /* OEM table identification */ \ 79 uint32_t oem_revision; /* OEM revision number */ \ 80 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */ \ 81 uint32_t asl_compiler_revision; /* ASL compiler revision number */ 82 83 84 struct AcpiTableHeader /* ACPI common table header */ 85 { 86 ACPI_TABLE_HEADER_DEF 87 } QEMU_PACKED; 88 typedef struct AcpiTableHeader AcpiTableHeader; 89 90 /* 91 * ACPI Fixed ACPI Description Table (FADT) 92 */ 93 #define ACPI_FADT_COMMON_DEF /* FADT common definition */ \ 94 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \ 95 uint32_t firmware_ctrl; /* Physical address of FACS */ \ 96 uint32_t dsdt; /* Physical address of DSDT */ \ 97 uint8_t model; /* System Interrupt Model */ \ 98 uint8_t reserved1; /* Reserved */ \ 99 uint16_t sci_int; /* System vector of SCI interrupt */ \ 100 uint32_t smi_cmd; /* Port address of SMI command port */ \ 101 uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ \ 102 uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ \ 103 /* Value to write to SMI CMD to enter S4BIOS state */ \ 104 uint8_t S4bios_req; \ 105 uint8_t reserved2; /* Reserved - must be zero */ \ 106 /* Port address of Power Mgt 1a acpi_event Reg Blk */ \ 107 uint32_t pm1a_evt_blk; \ 108 /* Port address of Power Mgt 1b acpi_event Reg Blk */ \ 109 uint32_t pm1b_evt_blk; \ 110 uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ \ 111 uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ \ 112 uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ \ 113 uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \ 114 /* Port addr of General Purpose acpi_event 0 Reg Blk */ \ 115 uint32_t gpe0_blk; \ 116 /* Port addr of General Purpose acpi_event 1 Reg Blk */ \ 117 uint32_t gpe1_blk; \ 118 uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ \ 119 uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ \ 120 uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ \ 121 uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ \ 122 uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ \ 123 uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ \ 124 uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ \ 125 uint8_t reserved3; /* Reserved */ \ 126 uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ \ 127 uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ \ 128 uint16_t flush_size; /* Size of area read to flush caches */ \ 129 uint16_t flush_stride; /* Stride used in flushing caches */ \ 130 uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ \ 131 uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ \ 132 uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \ 133 uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \ 134 uint8_t century; /* Index to century in RTC CMOS RAM */ 135 136 struct AcpiFadtDescriptorRev1 137 { 138 ACPI_FADT_COMMON_DEF 139 uint8_t reserved4; /* Reserved */ 140 uint8_t reserved4a; /* Reserved */ 141 uint8_t reserved4b; /* Reserved */ 142 uint32_t flags; 143 } QEMU_PACKED; 144 typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1; 145 146 struct AcpiGenericAddress { 147 uint8_t space_id; /* Address space where struct or register exists */ 148 uint8_t bit_width; /* Size in bits of given register */ 149 uint8_t bit_offset; /* Bit offset within the register */ 150 uint8_t access_width; /* Minimum Access size (ACPI 3.0) */ 151 uint64_t address; /* 64-bit address of struct or register */ 152 } QEMU_PACKED; 153 154 struct AcpiFadtDescriptorRev5_1 { 155 ACPI_FADT_COMMON_DEF 156 /* IA-PC Boot Architecture Flags (see below for individual flags) */ 157 uint16_t boot_flags; 158 uint8_t reserved; /* Reserved, must be zero */ 159 /* Miscellaneous flag bits (see below for individual flags) */ 160 uint32_t flags; 161 /* 64-bit address of the Reset register */ 162 struct AcpiGenericAddress reset_register; 163 /* Value to write to the reset_register port to reset the system */ 164 uint8_t reset_value; 165 /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */ 166 uint16_t arm_boot_flags; 167 uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */ 168 uint64_t Xfacs; /* 64-bit physical address of FACS */ 169 uint64_t Xdsdt; /* 64-bit physical address of DSDT */ 170 /* 64-bit Extended Power Mgt 1a Event Reg Blk address */ 171 struct AcpiGenericAddress xpm1a_event_block; 172 /* 64-bit Extended Power Mgt 1b Event Reg Blk address */ 173 struct AcpiGenericAddress xpm1b_event_block; 174 /* 64-bit Extended Power Mgt 1a Control Reg Blk address */ 175 struct AcpiGenericAddress xpm1a_control_block; 176 /* 64-bit Extended Power Mgt 1b Control Reg Blk address */ 177 struct AcpiGenericAddress xpm1b_control_block; 178 /* 64-bit Extended Power Mgt 2 Control Reg Blk address */ 179 struct AcpiGenericAddress xpm2_control_block; 180 /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */ 181 struct AcpiGenericAddress xpm_timer_block; 182 /* 64-bit Extended General Purpose Event 0 Reg Blk address */ 183 struct AcpiGenericAddress xgpe0_block; 184 /* 64-bit Extended General Purpose Event 1 Reg Blk address */ 185 struct AcpiGenericAddress xgpe1_block; 186 /* 64-bit Sleep Control register (ACPI 5.0) */ 187 struct AcpiGenericAddress sleep_control; 188 /* 64-bit Sleep Status register (ACPI 5.0) */ 189 struct AcpiGenericAddress sleep_status; 190 } QEMU_PACKED; 191 192 typedef struct AcpiFadtDescriptorRev5_1 AcpiFadtDescriptorRev5_1; 193 194 enum { 195 ACPI_FADT_ARM_USE_PSCI_G_0_2 = 0, 196 ACPI_FADT_ARM_PSCI_USE_HVC = 1, 197 }; 198 199 /* 200 * ACPI 1.0 Root System Description Table (RSDT) 201 */ 202 struct AcpiRsdtDescriptorRev1 203 { 204 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 205 uint32_t table_offset_entry[0]; /* Array of pointers to other */ 206 /* ACPI tables */ 207 } QEMU_PACKED; 208 typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1; 209 210 /* 211 * ACPI 1.0 Firmware ACPI Control Structure (FACS) 212 */ 213 struct AcpiFacsDescriptorRev1 214 { 215 uint32_t signature; /* ACPI Signature */ 216 uint32_t length; /* Length of structure, in bytes */ 217 uint32_t hardware_signature; /* Hardware configuration signature */ 218 uint32_t firmware_waking_vector; /* ACPI OS waking vector */ 219 uint32_t global_lock; /* Global Lock */ 220 uint32_t flags; 221 uint8_t resverved3 [40]; /* Reserved - must be zero */ 222 } QEMU_PACKED; 223 typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1; 224 225 /* 226 * Differentiated System Description Table (DSDT) 227 */ 228 229 /* 230 * MADT values and structures 231 */ 232 233 /* Values for MADT PCATCompat */ 234 235 #define ACPI_DUAL_PIC 0 236 #define ACPI_MULTIPLE_APIC 1 237 238 /* Master MADT */ 239 240 struct AcpiMultipleApicTable 241 { 242 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 243 uint32_t local_apic_address; /* Physical address of local APIC */ 244 uint32_t flags; 245 } QEMU_PACKED; 246 typedef struct AcpiMultipleApicTable AcpiMultipleApicTable; 247 248 /* Values for Type in APIC sub-headers */ 249 250 #define ACPI_APIC_PROCESSOR 0 251 #define ACPI_APIC_IO 1 252 #define ACPI_APIC_XRUPT_OVERRIDE 2 253 #define ACPI_APIC_NMI 3 254 #define ACPI_APIC_LOCAL_NMI 4 255 #define ACPI_APIC_ADDRESS_OVERRIDE 5 256 #define ACPI_APIC_IO_SAPIC 6 257 #define ACPI_APIC_LOCAL_SAPIC 7 258 #define ACPI_APIC_XRUPT_SOURCE 8 259 #define ACPI_APIC_LOCAL_X2APIC 9 260 #define ACPI_APIC_LOCAL_X2APIC_NMI 10 261 #define ACPI_APIC_GENERIC_INTERRUPT 11 262 #define ACPI_APIC_GENERIC_DISTRIBUTOR 12 263 #define ACPI_APIC_GENERIC_MSI_FRAME 13 264 #define ACPI_APIC_GENERIC_REDISTRIBUTOR 14 265 #define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */ 266 267 /* 268 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) 269 */ 270 #define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\ 271 uint8_t type; \ 272 uint8_t length; 273 274 /* Sub-structures for MADT */ 275 276 struct AcpiMadtProcessorApic 277 { 278 ACPI_SUB_HEADER_DEF 279 uint8_t processor_id; /* ACPI processor id */ 280 uint8_t local_apic_id; /* Processor's local APIC id */ 281 uint32_t flags; 282 } QEMU_PACKED; 283 typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic; 284 285 struct AcpiMadtIoApic 286 { 287 ACPI_SUB_HEADER_DEF 288 uint8_t io_apic_id; /* I/O APIC ID */ 289 uint8_t reserved; /* Reserved - must be zero */ 290 uint32_t address; /* APIC physical address */ 291 uint32_t interrupt; /* Global system interrupt where INTI 292 * lines start */ 293 } QEMU_PACKED; 294 typedef struct AcpiMadtIoApic AcpiMadtIoApic; 295 296 struct AcpiMadtIntsrcovr { 297 ACPI_SUB_HEADER_DEF 298 uint8_t bus; 299 uint8_t source; 300 uint32_t gsi; 301 uint16_t flags; 302 } QEMU_PACKED; 303 typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr; 304 305 struct AcpiMadtLocalNmi { 306 ACPI_SUB_HEADER_DEF 307 uint8_t processor_id; /* ACPI processor id */ 308 uint16_t flags; /* MPS INTI flags */ 309 uint8_t lint; /* Local APIC LINT# */ 310 } QEMU_PACKED; 311 typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi; 312 313 struct AcpiMadtGenericInterrupt { 314 ACPI_SUB_HEADER_DEF 315 uint16_t reserved; 316 uint32_t cpu_interface_number; 317 uint32_t uid; 318 uint32_t flags; 319 uint32_t parking_version; 320 uint32_t performance_interrupt; 321 uint64_t parked_address; 322 uint64_t base_address; 323 uint64_t gicv_base_address; 324 uint64_t gich_base_address; 325 uint32_t vgic_interrupt; 326 uint64_t gicr_base_address; 327 uint64_t arm_mpidr; 328 } QEMU_PACKED; 329 330 typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt; 331 332 struct AcpiMadtGenericDistributor { 333 ACPI_SUB_HEADER_DEF 334 uint16_t reserved; 335 uint32_t gic_id; 336 uint64_t base_address; 337 uint32_t global_irq_base; 338 uint32_t reserved2; 339 } QEMU_PACKED; 340 341 typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor; 342 343 /* 344 * Generic Timer Description Table (GTDT) 345 */ 346 347 #define ACPI_GTDT_INTERRUPT_MODE (1 << 0) 348 #define ACPI_GTDT_INTERRUPT_POLARITY (1 << 1) 349 #define ACPI_GTDT_ALWAYS_ON (1 << 2) 350 351 /* Triggering */ 352 353 #define ACPI_LEVEL_SENSITIVE ((uint8_t) 0x00) 354 #define ACPI_EDGE_SENSITIVE ((uint8_t) 0x01) 355 356 /* Polarity */ 357 358 #define ACPI_ACTIVE_HIGH ((uint8_t) 0x00) 359 #define ACPI_ACTIVE_LOW ((uint8_t) 0x01) 360 #define ACPI_ACTIVE_BOTH ((uint8_t) 0x02) 361 362 struct AcpiGenericTimerTable { 363 ACPI_TABLE_HEADER_DEF 364 uint64_t counter_block_addresss; 365 uint32_t reserved; 366 uint32_t secure_el1_interrupt; 367 uint32_t secure_el1_flags; 368 uint32_t non_secure_el1_interrupt; 369 uint32_t non_secure_el1_flags; 370 uint32_t virtual_timer_interrupt; 371 uint32_t virtual_timer_flags; 372 uint32_t non_secure_el2_interrupt; 373 uint32_t non_secure_el2_flags; 374 uint64_t counter_read_block_address; 375 uint32_t platform_timer_count; 376 uint32_t platform_timer_offset; 377 } QEMU_PACKED; 378 typedef struct AcpiGenericTimerTable AcpiGenericTimerTable; 379 380 /* 381 * HPET Description Table 382 */ 383 struct Acpi20Hpet { 384 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 385 uint32_t timer_block_id; 386 Acpi20GenericAddress addr; 387 uint8_t hpet_number; 388 uint16_t min_tick; 389 uint8_t page_protect; 390 } QEMU_PACKED; 391 typedef struct Acpi20Hpet Acpi20Hpet; 392 393 /* 394 * SRAT (NUMA topology description) table 395 */ 396 397 struct AcpiSystemResourceAffinityTable 398 { 399 ACPI_TABLE_HEADER_DEF 400 uint32_t reserved1; 401 uint32_t reserved2[2]; 402 } QEMU_PACKED; 403 typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable; 404 405 #define ACPI_SRAT_PROCESSOR 0 406 #define ACPI_SRAT_MEMORY 1 407 408 struct AcpiSratProcessorAffinity 409 { 410 ACPI_SUB_HEADER_DEF 411 uint8_t proximity_lo; 412 uint8_t local_apic_id; 413 uint32_t flags; 414 uint8_t local_sapic_eid; 415 uint8_t proximity_hi[3]; 416 uint32_t reserved; 417 } QEMU_PACKED; 418 typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity; 419 420 struct AcpiSratMemoryAffinity 421 { 422 ACPI_SUB_HEADER_DEF 423 uint8_t proximity[4]; 424 uint16_t reserved1; 425 uint64_t base_addr; 426 uint64_t range_length; 427 uint32_t reserved2; 428 uint32_t flags; 429 uint32_t reserved3[2]; 430 } QEMU_PACKED; 431 typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity; 432 433 /* PCI fw r3.0 MCFG table. */ 434 /* Subtable */ 435 struct AcpiMcfgAllocation { 436 uint64_t address; /* Base address, processor-relative */ 437 uint16_t pci_segment; /* PCI segment group number */ 438 uint8_t start_bus_number; /* Starting PCI Bus number */ 439 uint8_t end_bus_number; /* Final PCI Bus number */ 440 uint32_t reserved; 441 } QEMU_PACKED; 442 typedef struct AcpiMcfgAllocation AcpiMcfgAllocation; 443 444 struct AcpiTableMcfg { 445 ACPI_TABLE_HEADER_DEF; 446 uint8_t reserved[8]; 447 AcpiMcfgAllocation allocation[0]; 448 } QEMU_PACKED; 449 typedef struct AcpiTableMcfg AcpiTableMcfg; 450 451 /* 452 * TCPA Description Table 453 */ 454 struct Acpi20Tcpa { 455 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 456 uint16_t platform_class; 457 uint32_t log_area_minimum_length; 458 uint64_t log_area_start_address; 459 } QEMU_PACKED; 460 typedef struct Acpi20Tcpa Acpi20Tcpa; 461 462 /* DMAR - DMA Remapping table r2.2 */ 463 struct AcpiTableDmar { 464 ACPI_TABLE_HEADER_DEF 465 uint8_t host_address_width; /* Maximum DMA physical addressability */ 466 uint8_t flags; 467 uint8_t reserved[10]; 468 } QEMU_PACKED; 469 typedef struct AcpiTableDmar AcpiTableDmar; 470 471 /* Masks for Flags field above */ 472 #define ACPI_DMAR_INTR_REMAP 1 473 #define ACPI_DMAR_X2APIC_OPT_OUT (1 << 1) 474 475 /* Values for sub-structure type for DMAR */ 476 enum { 477 ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, /* DRHD */ 478 ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, /* RMRR */ 479 ACPI_DMAR_TYPE_ATSR = 2, /* ATSR */ 480 ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, /* RHSR */ 481 ACPI_DMAR_TYPE_ANDD = 4, /* ANDD */ 482 ACPI_DMAR_TYPE_RESERVED = 5 /* Reserved for furture use */ 483 }; 484 485 /* 486 * Sub-structures for DMAR 487 */ 488 /* Type 0: Hardware Unit Definition */ 489 struct AcpiDmarHardwareUnit { 490 uint16_t type; 491 uint16_t length; 492 uint8_t flags; 493 uint8_t reserved; 494 uint16_t pci_segment; /* The PCI Segment associated with this unit */ 495 uint64_t address; /* Base address of remapping hardware register-set */ 496 } QEMU_PACKED; 497 typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit; 498 499 /* Masks for Flags field above */ 500 #define ACPI_DMAR_INCLUDE_PCI_ALL 1 501 502 #endif 503