1 /* 2 * Generic intermediate code generation. 3 * 4 * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef EXEC__TRANSLATOR_H 11 #define EXEC__TRANSLATOR_H 12 13 /* 14 * Include this header from a target-specific file, and add a 15 * 16 * DisasContextBase base; 17 * 18 * member in your target-specific DisasContext. 19 */ 20 21 #include "qemu/bswap.h" 22 #include "exec/cpu-common.h" 23 #include "exec/cpu-defs.h" 24 #include "exec/abi_ptr.h" 25 #include "cpu.h" 26 27 /** 28 * gen_intermediate_code 29 * @cpu: cpu context 30 * @tb: translation block 31 * @max_insns: max number of instructions to translate 32 * @pc: guest virtual program counter address 33 * @host_pc: host physical program counter address 34 * 35 * This function must be provided by the target, which should create 36 * the target-specific DisasContext, and then invoke translator_loop. 37 */ 38 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, 39 vaddr pc, void *host_pc); 40 41 /** 42 * DisasJumpType: 43 * @DISAS_NEXT: Next instruction in program order. 44 * @DISAS_TOO_MANY: Too many instructions translated. 45 * @DISAS_NORETURN: Following code is dead. 46 * @DISAS_TARGET_*: Start of target-specific conditions. 47 * 48 * What instruction to disassemble next. 49 */ 50 typedef enum DisasJumpType { 51 DISAS_NEXT, 52 DISAS_TOO_MANY, 53 DISAS_NORETURN, 54 DISAS_TARGET_0, 55 DISAS_TARGET_1, 56 DISAS_TARGET_2, 57 DISAS_TARGET_3, 58 DISAS_TARGET_4, 59 DISAS_TARGET_5, 60 DISAS_TARGET_6, 61 DISAS_TARGET_7, 62 DISAS_TARGET_8, 63 DISAS_TARGET_9, 64 DISAS_TARGET_10, 65 DISAS_TARGET_11, 66 } DisasJumpType; 67 68 /** 69 * DisasContextBase: 70 * @tb: Translation block for this disassembly. 71 * @pc_first: Address of first guest instruction in this TB. 72 * @pc_next: Address of next guest instruction in this TB (current during 73 * disassembly). 74 * @is_jmp: What instruction to disassemble next. 75 * @num_insns: Number of translated instructions (including current). 76 * @max_insns: Maximum number of instructions to be translated in this TB. 77 * @singlestep_enabled: "Hardware" single stepping enabled. 78 * @saved_can_do_io: Known value of cpu->neg.can_do_io, or -1 for unknown. 79 * @plugin_enabled: TCG plugin enabled in this TB. 80 * @insn_start: The last op emitted by the insn_start hook, 81 * which is expected to be INDEX_op_insn_start. 82 * 83 * Architecture-agnostic disassembly context. 84 */ 85 typedef struct DisasContextBase { 86 TranslationBlock *tb; 87 vaddr pc_first; 88 vaddr pc_next; 89 DisasJumpType is_jmp; 90 int num_insns; 91 int max_insns; 92 bool singlestep_enabled; 93 bool plugin_enabled; 94 struct TCGOp *insn_start; 95 void *host_addr[2]; 96 } DisasContextBase; 97 98 /** 99 * TranslatorOps: 100 * @init_disas_context: 101 * Initialize the target-specific portions of DisasContext struct. 102 * The generic DisasContextBase has already been initialized. 103 * 104 * @tb_start: 105 * Emit any code required before the start of the main loop, 106 * after the generic gen_tb_start(). 107 * 108 * @insn_start: 109 * Emit the tcg_gen_insn_start opcode. 110 * 111 * @translate_insn: 112 * Disassemble one instruction and set db->pc_next for the start 113 * of the following instruction. Set db->is_jmp as necessary to 114 * terminate the main loop. 115 * 116 * @tb_stop: 117 * Emit any opcodes required to exit the TB, based on db->is_jmp. 118 * 119 * @disas_log: 120 * Print instruction disassembly to log. 121 */ 122 typedef struct TranslatorOps { 123 void (*init_disas_context)(DisasContextBase *db, CPUState *cpu); 124 void (*tb_start)(DisasContextBase *db, CPUState *cpu); 125 void (*insn_start)(DisasContextBase *db, CPUState *cpu); 126 void (*translate_insn)(DisasContextBase *db, CPUState *cpu); 127 void (*tb_stop)(DisasContextBase *db, CPUState *cpu); 128 void (*disas_log)(const DisasContextBase *db, CPUState *cpu, FILE *f); 129 } TranslatorOps; 130 131 /** 132 * translator_loop: 133 * @cpu: Target vCPU. 134 * @tb: Translation block. 135 * @max_insns: Maximum number of insns to translate. 136 * @pc: guest virtual program counter address 137 * @host_pc: host physical program counter address 138 * @ops: Target-specific operations. 139 * @db: Disassembly context. 140 * 141 * Generic translator loop. 142 * 143 * Translation will stop in the following cases (in order): 144 * - When is_jmp set by #TranslatorOps::breakpoint_check. 145 * - set to DISAS_TOO_MANY exits after translating one more insn 146 * - set to any other value than DISAS_NEXT exits immediately. 147 * - When is_jmp set by #TranslatorOps::translate_insn. 148 * - set to any value other than DISAS_NEXT exits immediately. 149 * - When the TCG operation buffer is full. 150 * - When single-stepping is enabled (system-wide or on the current vCPU). 151 * - When too many instructions have been translated. 152 */ 153 void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, 154 vaddr pc, void *host_pc, const TranslatorOps *ops, 155 DisasContextBase *db); 156 157 /** 158 * translator_use_goto_tb 159 * @db: Disassembly context 160 * @dest: target pc of the goto 161 * 162 * Return true if goto_tb is allowed between the current TB 163 * and the destination PC. 164 */ 165 bool translator_use_goto_tb(DisasContextBase *db, vaddr dest); 166 167 /** 168 * translator_io_start 169 * @db: Disassembly context 170 * 171 * If icount is enabled, set cpu->can_do_io, adjust db->is_jmp to 172 * DISAS_TOO_MANY if it is still DISAS_NEXT, and return true. 173 * Otherwise return false. 174 */ 175 bool translator_io_start(DisasContextBase *db); 176 177 /* 178 * Translator Load Functions 179 * 180 * These are intended to replace the direct usage of the cpu_ld*_code 181 * functions and are mandatory for front-ends that have been migrated 182 * to the common translator_loop. These functions are only intended 183 * to be called from the translation stage and should not be called 184 * from helper functions. Those functions should be converted to encode 185 * the relevant information at translation time. 186 */ 187 188 uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc); 189 uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc); 190 uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc); 191 uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc); 192 193 static inline uint16_t 194 translator_lduw_swap(CPUArchState *env, DisasContextBase *db, 195 abi_ptr pc, bool do_swap) 196 { 197 uint16_t ret = translator_lduw(env, db, pc); 198 if (do_swap) { 199 ret = bswap16(ret); 200 } 201 return ret; 202 } 203 204 static inline uint32_t 205 translator_ldl_swap(CPUArchState *env, DisasContextBase *db, 206 abi_ptr pc, bool do_swap) 207 { 208 uint32_t ret = translator_ldl(env, db, pc); 209 if (do_swap) { 210 ret = bswap32(ret); 211 } 212 return ret; 213 } 214 215 static inline uint64_t 216 translator_ldq_swap(CPUArchState *env, DisasContextBase *db, 217 abi_ptr pc, bool do_swap) 218 { 219 uint64_t ret = translator_ldq(env, db, pc); 220 if (do_swap) { 221 ret = bswap64(ret); 222 } 223 return ret; 224 } 225 226 /** 227 * translator_fake_ldb - fake instruction load 228 * @insn8: byte of instruction 229 * @pc: program counter of instruction 230 * 231 * This is a special case helper used where the instruction we are 232 * about to translate comes from somewhere else (e.g. being 233 * re-synthesised for s390x "ex"). It ensures we update other areas of 234 * the translator with details of the executed instruction. 235 */ 236 void translator_fake_ldb(uint8_t insn8, abi_ptr pc); 237 238 /* 239 * Return whether addr is on the same page as where disassembly started. 240 * Translators can use this to enforce the rule that only single-insn 241 * translation blocks are allowed to cross page boundaries. 242 */ 243 static inline bool is_same_page(const DisasContextBase *db, vaddr addr) 244 { 245 return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) == 0; 246 } 247 248 #endif /* EXEC__TRANSLATOR_H */ 249