1 /* 2 * Generic intermediate code generation. 3 * 4 * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef EXEC__TRANSLATOR_H 11 #define EXEC__TRANSLATOR_H 12 13 /* 14 * Include this header from a target-specific file, and add a 15 * 16 * DisasContextBase base; 17 * 18 * member in your target-specific DisasContext. 19 */ 20 21 #include "qemu/bswap.h" 22 #include "exec/cpu_ldst.h" /* for abi_ptr */ 23 24 /** 25 * gen_intermediate_code 26 * @cpu: cpu context 27 * @tb: translation block 28 * @max_insns: max number of instructions to translate 29 * @pc: guest virtual program counter address 30 * @host_pc: host physical program counter address 31 * 32 * This function must be provided by the target, which should create 33 * the target-specific DisasContext, and then invoke translator_loop. 34 */ 35 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, 36 target_ulong pc, void *host_pc); 37 38 /** 39 * DisasJumpType: 40 * @DISAS_NEXT: Next instruction in program order. 41 * @DISAS_TOO_MANY: Too many instructions translated. 42 * @DISAS_NORETURN: Following code is dead. 43 * @DISAS_TARGET_*: Start of target-specific conditions. 44 * 45 * What instruction to disassemble next. 46 */ 47 typedef enum DisasJumpType { 48 DISAS_NEXT, 49 DISAS_TOO_MANY, 50 DISAS_NORETURN, 51 DISAS_TARGET_0, 52 DISAS_TARGET_1, 53 DISAS_TARGET_2, 54 DISAS_TARGET_3, 55 DISAS_TARGET_4, 56 DISAS_TARGET_5, 57 DISAS_TARGET_6, 58 DISAS_TARGET_7, 59 DISAS_TARGET_8, 60 DISAS_TARGET_9, 61 DISAS_TARGET_10, 62 DISAS_TARGET_11, 63 } DisasJumpType; 64 65 /** 66 * DisasContextBase: 67 * @tb: Translation block for this disassembly. 68 * @pc_first: Address of first guest instruction in this TB. 69 * @pc_next: Address of next guest instruction in this TB (current during 70 * disassembly). 71 * @is_jmp: What instruction to disassemble next. 72 * @num_insns: Number of translated instructions (including current). 73 * @max_insns: Maximum number of instructions to be translated in this TB. 74 * @singlestep_enabled: "Hardware" single stepping enabled. 75 * 76 * Architecture-agnostic disassembly context. 77 */ 78 typedef struct DisasContextBase { 79 TranslationBlock *tb; 80 target_ulong pc_first; 81 target_ulong pc_next; 82 DisasJumpType is_jmp; 83 int num_insns; 84 int max_insns; 85 bool singlestep_enabled; 86 void *host_addr[2]; 87 } DisasContextBase; 88 89 /** 90 * TranslatorOps: 91 * @init_disas_context: 92 * Initialize the target-specific portions of DisasContext struct. 93 * The generic DisasContextBase has already been initialized. 94 * 95 * @tb_start: 96 * Emit any code required before the start of the main loop, 97 * after the generic gen_tb_start(). 98 * 99 * @insn_start: 100 * Emit the tcg_gen_insn_start opcode. 101 * 102 * @translate_insn: 103 * Disassemble one instruction and set db->pc_next for the start 104 * of the following instruction. Set db->is_jmp as necessary to 105 * terminate the main loop. 106 * 107 * @tb_stop: 108 * Emit any opcodes required to exit the TB, based on db->is_jmp. 109 * 110 * @disas_log: 111 * Print instruction disassembly to log. 112 */ 113 typedef struct TranslatorOps { 114 void (*init_disas_context)(DisasContextBase *db, CPUState *cpu); 115 void (*tb_start)(DisasContextBase *db, CPUState *cpu); 116 void (*insn_start)(DisasContextBase *db, CPUState *cpu); 117 void (*translate_insn)(DisasContextBase *db, CPUState *cpu); 118 void (*tb_stop)(DisasContextBase *db, CPUState *cpu); 119 void (*disas_log)(const DisasContextBase *db, CPUState *cpu, FILE *f); 120 } TranslatorOps; 121 122 /** 123 * translator_loop: 124 * @cpu: Target vCPU. 125 * @tb: Translation block. 126 * @max_insns: Maximum number of insns to translate. 127 * @pc: guest virtual program counter address 128 * @host_pc: host physical program counter address 129 * @ops: Target-specific operations. 130 * @db: Disassembly context. 131 * 132 * Generic translator loop. 133 * 134 * Translation will stop in the following cases (in order): 135 * - When is_jmp set by #TranslatorOps::breakpoint_check. 136 * - set to DISAS_TOO_MANY exits after translating one more insn 137 * - set to any other value than DISAS_NEXT exits immediately. 138 * - When is_jmp set by #TranslatorOps::translate_insn. 139 * - set to any value other than DISAS_NEXT exits immediately. 140 * - When the TCG operation buffer is full. 141 * - When single-stepping is enabled (system-wide or on the current vCPU). 142 * - When too many instructions have been translated. 143 */ 144 void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, 145 target_ulong pc, void *host_pc, 146 const TranslatorOps *ops, DisasContextBase *db); 147 148 /** 149 * translator_use_goto_tb 150 * @db: Disassembly context 151 * @dest: target pc of the goto 152 * 153 * Return true if goto_tb is allowed between the current TB 154 * and the destination PC. 155 */ 156 bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest); 157 158 /** 159 * translator_io_start 160 * @db: Disassembly context 161 * 162 * If icount is enabled, set cpu->can_to_io, adjust db->is_jmp to 163 * DISAS_TOO_MANY if it is still DISAS_NEXT, and return true. 164 * Otherwise return false. 165 */ 166 bool translator_io_start(DisasContextBase *db); 167 168 /* 169 * Translator Load Functions 170 * 171 * These are intended to replace the direct usage of the cpu_ld*_code 172 * functions and are mandatory for front-ends that have been migrated 173 * to the common translator_loop. These functions are only intended 174 * to be called from the translation stage and should not be called 175 * from helper functions. Those functions should be converted to encode 176 * the relevant information at translation time. 177 */ 178 179 uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc); 180 uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc); 181 uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc); 182 uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc); 183 184 static inline uint16_t 185 translator_lduw_swap(CPUArchState *env, DisasContextBase *db, 186 abi_ptr pc, bool do_swap) 187 { 188 uint16_t ret = translator_lduw(env, db, pc); 189 if (do_swap) { 190 ret = bswap16(ret); 191 } 192 return ret; 193 } 194 195 static inline uint32_t 196 translator_ldl_swap(CPUArchState *env, DisasContextBase *db, 197 abi_ptr pc, bool do_swap) 198 { 199 uint32_t ret = translator_ldl(env, db, pc); 200 if (do_swap) { 201 ret = bswap32(ret); 202 } 203 return ret; 204 } 205 206 static inline uint64_t 207 translator_ldq_swap(CPUArchState *env, DisasContextBase *db, 208 abi_ptr pc, bool do_swap) 209 { 210 uint64_t ret = translator_ldq(env, db, pc); 211 if (do_swap) { 212 ret = bswap64(ret); 213 } 214 return ret; 215 } 216 217 /** 218 * translator_fake_ldb - fake instruction load 219 * @insn8: byte of instruction 220 * @pc: program counter of instruction 221 * 222 * This is a special case helper used where the instruction we are 223 * about to translate comes from somewhere else (e.g. being 224 * re-synthesised for s390x "ex"). It ensures we update other areas of 225 * the translator with details of the executed instruction. 226 */ 227 void translator_fake_ldb(uint8_t insn8, abi_ptr pc); 228 229 /* 230 * Return whether addr is on the same page as where disassembly started. 231 * Translators can use this to enforce the rule that only single-insn 232 * translation blocks are allowed to cross page boundaries. 233 */ 234 static inline bool is_same_page(const DisasContextBase *db, target_ulong addr) 235 { 236 return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) == 0; 237 } 238 239 #endif /* EXEC__TRANSLATOR_H */ 240