1 /* 2 * Generic intermediate code generation. 3 * 4 * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef EXEC__TRANSLATOR_H 11 #define EXEC__TRANSLATOR_H 12 13 /* 14 * Include this header from a target-specific file, and add a 15 * 16 * DisasContextBase base; 17 * 18 * member in your target-specific DisasContext. 19 */ 20 21 #include "qemu/bswap.h" 22 #include "exec/cpu_ldst.h" /* for abi_ptr */ 23 24 /** 25 * gen_intermediate_code 26 * @cpu: cpu context 27 * @tb: translation block 28 * @max_insns: max number of instructions to translate 29 * @pc: guest virtual program counter address 30 * @host_pc: host physical program counter address 31 * 32 * This function must be provided by the target, which should create 33 * the target-specific DisasContext, and then invoke translator_loop. 34 */ 35 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, 36 vaddr pc, void *host_pc); 37 38 /** 39 * DisasJumpType: 40 * @DISAS_NEXT: Next instruction in program order. 41 * @DISAS_TOO_MANY: Too many instructions translated. 42 * @DISAS_NORETURN: Following code is dead. 43 * @DISAS_TARGET_*: Start of target-specific conditions. 44 * 45 * What instruction to disassemble next. 46 */ 47 typedef enum DisasJumpType { 48 DISAS_NEXT, 49 DISAS_TOO_MANY, 50 DISAS_NORETURN, 51 DISAS_TARGET_0, 52 DISAS_TARGET_1, 53 DISAS_TARGET_2, 54 DISAS_TARGET_3, 55 DISAS_TARGET_4, 56 DISAS_TARGET_5, 57 DISAS_TARGET_6, 58 DISAS_TARGET_7, 59 DISAS_TARGET_8, 60 DISAS_TARGET_9, 61 DISAS_TARGET_10, 62 DISAS_TARGET_11, 63 } DisasJumpType; 64 65 /** 66 * DisasContextBase: 67 * @tb: Translation block for this disassembly. 68 * @pc_first: Address of first guest instruction in this TB. 69 * @pc_next: Address of next guest instruction in this TB (current during 70 * disassembly). 71 * @is_jmp: What instruction to disassemble next. 72 * @num_insns: Number of translated instructions (including current). 73 * @max_insns: Maximum number of instructions to be translated in this TB. 74 * @singlestep_enabled: "Hardware" single stepping enabled. 75 * @saved_can_do_io: Known value of cpu->neg.can_do_io, or -1 for unknown. 76 * @plugin_enabled: TCG plugin enabled in this TB. 77 * @insn_start: The last op emitted by the insn_start hook, 78 * which is expected to be INDEX_op_insn_start. 79 * 80 * Architecture-agnostic disassembly context. 81 */ 82 typedef struct DisasContextBase { 83 TranslationBlock *tb; 84 vaddr pc_first; 85 vaddr pc_next; 86 DisasJumpType is_jmp; 87 int num_insns; 88 int max_insns; 89 bool singlestep_enabled; 90 bool plugin_enabled; 91 struct TCGOp *insn_start; 92 void *host_addr[2]; 93 } DisasContextBase; 94 95 /** 96 * TranslatorOps: 97 * @init_disas_context: 98 * Initialize the target-specific portions of DisasContext struct. 99 * The generic DisasContextBase has already been initialized. 100 * 101 * @tb_start: 102 * Emit any code required before the start of the main loop, 103 * after the generic gen_tb_start(). 104 * 105 * @insn_start: 106 * Emit the tcg_gen_insn_start opcode. 107 * 108 * @translate_insn: 109 * Disassemble one instruction and set db->pc_next for the start 110 * of the following instruction. Set db->is_jmp as necessary to 111 * terminate the main loop. 112 * 113 * @tb_stop: 114 * Emit any opcodes required to exit the TB, based on db->is_jmp. 115 * 116 * @disas_log: 117 * Print instruction disassembly to log. 118 */ 119 typedef struct TranslatorOps { 120 void (*init_disas_context)(DisasContextBase *db, CPUState *cpu); 121 void (*tb_start)(DisasContextBase *db, CPUState *cpu); 122 void (*insn_start)(DisasContextBase *db, CPUState *cpu); 123 void (*translate_insn)(DisasContextBase *db, CPUState *cpu); 124 void (*tb_stop)(DisasContextBase *db, CPUState *cpu); 125 void (*disas_log)(const DisasContextBase *db, CPUState *cpu, FILE *f); 126 } TranslatorOps; 127 128 /** 129 * translator_loop: 130 * @cpu: Target vCPU. 131 * @tb: Translation block. 132 * @max_insns: Maximum number of insns to translate. 133 * @pc: guest virtual program counter address 134 * @host_pc: host physical program counter address 135 * @ops: Target-specific operations. 136 * @db: Disassembly context. 137 * 138 * Generic translator loop. 139 * 140 * Translation will stop in the following cases (in order): 141 * - When is_jmp set by #TranslatorOps::breakpoint_check. 142 * - set to DISAS_TOO_MANY exits after translating one more insn 143 * - set to any other value than DISAS_NEXT exits immediately. 144 * - When is_jmp set by #TranslatorOps::translate_insn. 145 * - set to any value other than DISAS_NEXT exits immediately. 146 * - When the TCG operation buffer is full. 147 * - When single-stepping is enabled (system-wide or on the current vCPU). 148 * - When too many instructions have been translated. 149 */ 150 void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, 151 vaddr pc, void *host_pc, const TranslatorOps *ops, 152 DisasContextBase *db); 153 154 /** 155 * translator_use_goto_tb 156 * @db: Disassembly context 157 * @dest: target pc of the goto 158 * 159 * Return true if goto_tb is allowed between the current TB 160 * and the destination PC. 161 */ 162 bool translator_use_goto_tb(DisasContextBase *db, vaddr dest); 163 164 /** 165 * translator_io_start 166 * @db: Disassembly context 167 * 168 * If icount is enabled, set cpu->can_do_io, adjust db->is_jmp to 169 * DISAS_TOO_MANY if it is still DISAS_NEXT, and return true. 170 * Otherwise return false. 171 */ 172 bool translator_io_start(DisasContextBase *db); 173 174 /* 175 * Translator Load Functions 176 * 177 * These are intended to replace the direct usage of the cpu_ld*_code 178 * functions and are mandatory for front-ends that have been migrated 179 * to the common translator_loop. These functions are only intended 180 * to be called from the translation stage and should not be called 181 * from helper functions. Those functions should be converted to encode 182 * the relevant information at translation time. 183 */ 184 185 uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc); 186 uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc); 187 uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc); 188 uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc); 189 190 static inline uint16_t 191 translator_lduw_swap(CPUArchState *env, DisasContextBase *db, 192 abi_ptr pc, bool do_swap) 193 { 194 uint16_t ret = translator_lduw(env, db, pc); 195 if (do_swap) { 196 ret = bswap16(ret); 197 } 198 return ret; 199 } 200 201 static inline uint32_t 202 translator_ldl_swap(CPUArchState *env, DisasContextBase *db, 203 abi_ptr pc, bool do_swap) 204 { 205 uint32_t ret = translator_ldl(env, db, pc); 206 if (do_swap) { 207 ret = bswap32(ret); 208 } 209 return ret; 210 } 211 212 static inline uint64_t 213 translator_ldq_swap(CPUArchState *env, DisasContextBase *db, 214 abi_ptr pc, bool do_swap) 215 { 216 uint64_t ret = translator_ldq(env, db, pc); 217 if (do_swap) { 218 ret = bswap64(ret); 219 } 220 return ret; 221 } 222 223 /** 224 * translator_fake_ldb - fake instruction load 225 * @insn8: byte of instruction 226 * @pc: program counter of instruction 227 * 228 * This is a special case helper used where the instruction we are 229 * about to translate comes from somewhere else (e.g. being 230 * re-synthesised for s390x "ex"). It ensures we update other areas of 231 * the translator with details of the executed instruction. 232 */ 233 void translator_fake_ldb(uint8_t insn8, abi_ptr pc); 234 235 /* 236 * Return whether addr is on the same page as where disassembly started. 237 * Translators can use this to enforce the rule that only single-insn 238 * translation blocks are allowed to cross page boundaries. 239 */ 240 static inline bool is_same_page(const DisasContextBase *db, vaddr addr) 241 { 242 return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) == 0; 243 } 244 245 #endif /* EXEC__TRANSLATOR_H */ 246