1 /* 2 * internal execution defines for qemu 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef EXEC_ALL_H 21 #define EXEC_ALL_H 22 23 #include "cpu.h" 24 #ifdef CONFIG_TCG 25 #include "exec/cpu_ldst.h" 26 #endif 27 #include "exec/translation-block.h" 28 #include "qemu/clang-tsa.h" 29 30 /** 31 * cpu_unwind_state_data: 32 * @cpu: the cpu context 33 * @host_pc: the host pc within the translation 34 * @data: output data 35 * 36 * Attempt to load the the unwind state for a host pc occurring in 37 * translated code. If @host_pc is not in translated code, the 38 * function returns false; otherwise @data is loaded. 39 * This is the same unwind info as given to restore_state_to_opc. 40 */ 41 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); 42 43 /** 44 * cpu_restore_state: 45 * @cpu: the cpu context 46 * @host_pc: the host pc within the translation 47 * @return: true if state was restored, false otherwise 48 * 49 * Attempt to restore the state for a fault occurring in translated 50 * code. If @host_pc is not in translated code no state is 51 * restored and the function returns false. 52 */ 53 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); 54 55 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); 56 G_NORETURN void cpu_loop_exit(CPUState *cpu); 57 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); 58 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); 59 60 /** 61 * cpu_loop_exit_requested: 62 * @cpu: The CPU state to be tested 63 * 64 * Indicate if somebody asked for a return of the CPU to the main loop 65 * (e.g., via cpu_exit() or cpu_interrupt()). 66 * 67 * This is helpful for architectures that support interruptible 68 * instructions. After writing back all state to registers/memory, this 69 * call can be used to check if it makes sense to return to the main loop 70 * or to continue executing the interruptible instruction. 71 */ 72 static inline bool cpu_loop_exit_requested(CPUState *cpu) 73 { 74 return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0; 75 } 76 77 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 78 /* cputlb.c */ 79 /** 80 * tlb_init - initialize a CPU's TLB 81 * @cpu: CPU whose TLB should be initialized 82 */ 83 void tlb_init(CPUState *cpu); 84 /** 85 * tlb_destroy - destroy a CPU's TLB 86 * @cpu: CPU whose TLB should be destroyed 87 */ 88 void tlb_destroy(CPUState *cpu); 89 /** 90 * tlb_flush_page: 91 * @cpu: CPU whose TLB should be flushed 92 * @addr: virtual address of page to be flushed 93 * 94 * Flush one page from the TLB of the specified CPU, for all 95 * MMU indexes. 96 */ 97 void tlb_flush_page(CPUState *cpu, target_ulong addr); 98 /** 99 * tlb_flush_page_all_cpus: 100 * @cpu: src CPU of the flush 101 * @addr: virtual address of page to be flushed 102 * 103 * Flush one page from the TLB of the specified CPU, for all 104 * MMU indexes. 105 */ 106 void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr); 107 /** 108 * tlb_flush_page_all_cpus_synced: 109 * @cpu: src CPU of the flush 110 * @addr: virtual address of page to be flushed 111 * 112 * Flush one page from the TLB of the specified CPU, for all MMU 113 * indexes like tlb_flush_page_all_cpus except the source vCPUs work 114 * is scheduled as safe work meaning all flushes will be complete once 115 * the source vCPUs safe work is complete. This will depend on when 116 * the guests translation ends the TB. 117 */ 118 void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr); 119 /** 120 * tlb_flush: 121 * @cpu: CPU whose TLB should be flushed 122 * 123 * Flush the entire TLB for the specified CPU. Most CPU architectures 124 * allow the implementation to drop entries from the TLB at any time 125 * so this is generally safe. If more selective flushing is required 126 * use one of the other functions for efficiency. 127 */ 128 void tlb_flush(CPUState *cpu); 129 /** 130 * tlb_flush_all_cpus: 131 * @cpu: src CPU of the flush 132 */ 133 void tlb_flush_all_cpus(CPUState *src_cpu); 134 /** 135 * tlb_flush_all_cpus_synced: 136 * @cpu: src CPU of the flush 137 * 138 * Like tlb_flush_all_cpus except this except the source vCPUs work is 139 * scheduled as safe work meaning all flushes will be complete once 140 * the source vCPUs safe work is complete. This will depend on when 141 * the guests translation ends the TB. 142 */ 143 void tlb_flush_all_cpus_synced(CPUState *src_cpu); 144 /** 145 * tlb_flush_page_by_mmuidx: 146 * @cpu: CPU whose TLB should be flushed 147 * @addr: virtual address of page to be flushed 148 * @idxmap: bitmap of MMU indexes to flush 149 * 150 * Flush one page from the TLB of the specified CPU, for the specified 151 * MMU indexes. 152 */ 153 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, 154 uint16_t idxmap); 155 /** 156 * tlb_flush_page_by_mmuidx_all_cpus: 157 * @cpu: Originating CPU of the flush 158 * @addr: virtual address of page to be flushed 159 * @idxmap: bitmap of MMU indexes to flush 160 * 161 * Flush one page from the TLB of all CPUs, for the specified 162 * MMU indexes. 163 */ 164 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, 165 uint16_t idxmap); 166 /** 167 * tlb_flush_page_by_mmuidx_all_cpus_synced: 168 * @cpu: Originating CPU of the flush 169 * @addr: virtual address of page to be flushed 170 * @idxmap: bitmap of MMU indexes to flush 171 * 172 * Flush one page from the TLB of all CPUs, for the specified MMU 173 * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source 174 * vCPUs work is scheduled as safe work meaning all flushes will be 175 * complete once the source vCPUs safe work is complete. This will 176 * depend on when the guests translation ends the TB. 177 */ 178 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr, 179 uint16_t idxmap); 180 /** 181 * tlb_flush_by_mmuidx: 182 * @cpu: CPU whose TLB should be flushed 183 * @wait: If true ensure synchronisation by exiting the cpu_loop 184 * @idxmap: bitmap of MMU indexes to flush 185 * 186 * Flush all entries from the TLB of the specified CPU, for the specified 187 * MMU indexes. 188 */ 189 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); 190 /** 191 * tlb_flush_by_mmuidx_all_cpus: 192 * @cpu: Originating CPU of the flush 193 * @idxmap: bitmap of MMU indexes to flush 194 * 195 * Flush all entries from all TLBs of all CPUs, for the specified 196 * MMU indexes. 197 */ 198 void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap); 199 /** 200 * tlb_flush_by_mmuidx_all_cpus_synced: 201 * @cpu: Originating CPU of the flush 202 * @idxmap: bitmap of MMU indexes to flush 203 * 204 * Flush all entries from all TLBs of all CPUs, for the specified 205 * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source 206 * vCPUs work is scheduled as safe work meaning all flushes will be 207 * complete once the source vCPUs safe work is complete. This will 208 * depend on when the guests translation ends the TB. 209 */ 210 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); 211 212 /** 213 * tlb_flush_page_bits_by_mmuidx 214 * @cpu: CPU whose TLB should be flushed 215 * @addr: virtual address of page to be flushed 216 * @idxmap: bitmap of mmu indexes to flush 217 * @bits: number of significant bits in address 218 * 219 * Similar to tlb_flush_page_mask, but with a bitmap of indexes. 220 */ 221 void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, 222 uint16_t idxmap, unsigned bits); 223 224 /* Similarly, with broadcast and syncing. */ 225 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, 226 uint16_t idxmap, unsigned bits); 227 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced 228 (CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits); 229 230 /** 231 * tlb_flush_range_by_mmuidx 232 * @cpu: CPU whose TLB should be flushed 233 * @addr: virtual address of the start of the range to be flushed 234 * @len: length of range to be flushed 235 * @idxmap: bitmap of mmu indexes to flush 236 * @bits: number of significant bits in address 237 * 238 * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), 239 * comparing only the low @bits worth of each virtual page. 240 */ 241 void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, 242 target_ulong len, uint16_t idxmap, 243 unsigned bits); 244 245 /* Similarly, with broadcast and syncing. */ 246 void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, 247 target_ulong len, uint16_t idxmap, 248 unsigned bits); 249 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, 250 target_ulong addr, 251 target_ulong len, 252 uint16_t idxmap, 253 unsigned bits); 254 255 /** 256 * tlb_set_page_full: 257 * @cpu: CPU context 258 * @mmu_idx: mmu index of the tlb to modify 259 * @vaddr: virtual address of the entry to add 260 * @full: the details of the tlb entry 261 * 262 * Add an entry to @cpu tlb index @mmu_idx. All of the fields of 263 * @full must be filled, except for xlat_section, and constitute 264 * the complete description of the translated page. 265 * 266 * This is generally called by the target tlb_fill function after 267 * having performed a successful page table walk to find the physical 268 * address and attributes for the translation. 269 * 270 * At most one entry for a given virtual address is permitted. Only a 271 * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only 272 * used by tlb_flush_page. 273 */ 274 void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr, 275 CPUTLBEntryFull *full); 276 277 /** 278 * tlb_set_page_with_attrs: 279 * @cpu: CPU to add this TLB entry for 280 * @vaddr: virtual address of page to add entry for 281 * @paddr: physical address of the page 282 * @attrs: memory transaction attributes 283 * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) 284 * @mmu_idx: MMU index to insert TLB entry for 285 * @size: size of the page in bytes 286 * 287 * Add an entry to this CPU's TLB (a mapping from virtual address 288 * @vaddr to physical address @paddr) with the specified memory 289 * transaction attributes. This is generally called by the target CPU 290 * specific code after it has been called through the tlb_fill() 291 * entry point and performed a successful page table walk to find 292 * the physical address and attributes for the virtual address 293 * which provoked the TLB miss. 294 * 295 * At most one entry for a given virtual address is permitted. Only a 296 * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only 297 * used by tlb_flush_page. 298 */ 299 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, 300 hwaddr paddr, MemTxAttrs attrs, 301 int prot, int mmu_idx, target_ulong size); 302 /* tlb_set_page: 303 * 304 * This function is equivalent to calling tlb_set_page_with_attrs() 305 * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided 306 * as a convenience for CPUs which don't use memory transaction attributes. 307 */ 308 void tlb_set_page(CPUState *cpu, target_ulong vaddr, 309 hwaddr paddr, int prot, 310 int mmu_idx, target_ulong size); 311 #else 312 static inline void tlb_init(CPUState *cpu) 313 { 314 } 315 static inline void tlb_destroy(CPUState *cpu) 316 { 317 } 318 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) 319 { 320 } 321 static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) 322 { 323 } 324 static inline void tlb_flush_page_all_cpus_synced(CPUState *src, 325 target_ulong addr) 326 { 327 } 328 static inline void tlb_flush(CPUState *cpu) 329 { 330 } 331 static inline void tlb_flush_all_cpus(CPUState *src_cpu) 332 { 333 } 334 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) 335 { 336 } 337 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, 338 target_ulong addr, uint16_t idxmap) 339 { 340 } 341 342 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) 343 { 344 } 345 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, 346 target_ulong addr, 347 uint16_t idxmap) 348 { 349 } 350 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, 351 target_ulong addr, 352 uint16_t idxmap) 353 { 354 } 355 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap) 356 { 357 } 358 359 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, 360 uint16_t idxmap) 361 { 362 } 363 static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, 364 target_ulong addr, 365 uint16_t idxmap, 366 unsigned bits) 367 { 368 } 369 static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, 370 target_ulong addr, 371 uint16_t idxmap, 372 unsigned bits) 373 { 374 } 375 static inline void 376 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr, 377 uint16_t idxmap, unsigned bits) 378 { 379 } 380 static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, 381 target_ulong len, uint16_t idxmap, 382 unsigned bits) 383 { 384 } 385 static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, 386 target_ulong addr, 387 target_ulong len, 388 uint16_t idxmap, 389 unsigned bits) 390 { 391 } 392 static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, 393 target_ulong addr, 394 target_long len, 395 uint16_t idxmap, 396 unsigned bits) 397 { 398 } 399 #endif 400 /** 401 * probe_access: 402 * @env: CPUArchState 403 * @addr: guest virtual address to look up 404 * @size: size of the access 405 * @access_type: read, write or execute permission 406 * @mmu_idx: MMU index to use for lookup 407 * @retaddr: return address for unwinding 408 * 409 * Look up the guest virtual address @addr. Raise an exception if the 410 * page does not satisfy @access_type. Raise an exception if the 411 * access (@addr, @size) hits a watchpoint. For writes, mark a clean 412 * page as dirty. 413 * 414 * Finally, return the host address for a page that is backed by RAM, 415 * or NULL if the page requires I/O. 416 */ 417 void *probe_access(CPUArchState *env, target_ulong addr, int size, 418 MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); 419 420 static inline void *probe_write(CPUArchState *env, target_ulong addr, int size, 421 int mmu_idx, uintptr_t retaddr) 422 { 423 return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); 424 } 425 426 static inline void *probe_read(CPUArchState *env, target_ulong addr, int size, 427 int mmu_idx, uintptr_t retaddr) 428 { 429 return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); 430 } 431 432 /** 433 * probe_access_flags: 434 * @env: CPUArchState 435 * @addr: guest virtual address to look up 436 * @size: size of the access 437 * @access_type: read, write or execute permission 438 * @mmu_idx: MMU index to use for lookup 439 * @nonfault: suppress the fault 440 * @phost: return value for host address 441 * @retaddr: return address for unwinding 442 * 443 * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for 444 * the page, and storing the host address for RAM in @phost. 445 * 446 * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK. 447 * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags. 448 * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags. 449 * For simplicity, all "mmio-like" flags are folded to TLB_MMIO. 450 */ 451 int probe_access_flags(CPUArchState *env, target_ulong addr, int size, 452 MMUAccessType access_type, int mmu_idx, 453 bool nonfault, void **phost, uintptr_t retaddr); 454 455 #ifndef CONFIG_USER_ONLY 456 /** 457 * probe_access_full: 458 * Like probe_access_flags, except also return into @pfull. 459 * 460 * The CPUTLBEntryFull structure returned via @pfull is transient 461 * and must be consumed or copied immediately, before any further 462 * access or changes to TLB @mmu_idx. 463 */ 464 int probe_access_full(CPUArchState *env, target_ulong addr, int size, 465 MMUAccessType access_type, int mmu_idx, 466 bool nonfault, void **phost, 467 CPUTLBEntryFull **pfull, uintptr_t retaddr); 468 #endif 469 470 /* Hide the qatomic_read to make code a little easier on the eyes */ 471 static inline uint32_t tb_cflags(const TranslationBlock *tb) 472 { 473 return qatomic_read(&tb->cflags); 474 } 475 476 static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb) 477 { 478 #ifdef CONFIG_USER_ONLY 479 return tb->itree.start; 480 #else 481 return tb->page_addr[0]; 482 #endif 483 } 484 485 static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb) 486 { 487 #ifdef CONFIG_USER_ONLY 488 tb_page_addr_t next = tb->itree.last & TARGET_PAGE_MASK; 489 return next == (tb->itree.start & TARGET_PAGE_MASK) ? -1 : next; 490 #else 491 return tb->page_addr[1]; 492 #endif 493 } 494 495 static inline void tb_set_page_addr0(TranslationBlock *tb, 496 tb_page_addr_t addr) 497 { 498 #ifdef CONFIG_USER_ONLY 499 tb->itree.start = addr; 500 /* 501 * To begin, we record an interval of one byte. When the translation 502 * loop encounters a second page, the interval will be extended to 503 * include the first byte of the second page, which is sufficient to 504 * allow tb_page_addr1() above to work properly. The final corrected 505 * interval will be set by tb_page_add() from tb->size before the 506 * node is added to the interval tree. 507 */ 508 tb->itree.last = addr; 509 #else 510 tb->page_addr[0] = addr; 511 #endif 512 } 513 514 static inline void tb_set_page_addr1(TranslationBlock *tb, 515 tb_page_addr_t addr) 516 { 517 #ifdef CONFIG_USER_ONLY 518 /* Extend the interval to the first byte of the second page. See above. */ 519 tb->itree.last = addr; 520 #else 521 tb->page_addr[1] = addr; 522 #endif 523 } 524 525 /* current cflags for hashing/comparison */ 526 uint32_t curr_cflags(CPUState *cpu); 527 528 /* TranslationBlock invalidate API */ 529 #if defined(CONFIG_USER_ONLY) 530 void tb_invalidate_phys_addr(target_ulong addr); 531 #else 532 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs); 533 #endif 534 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); 535 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last); 536 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); 537 538 /* GETPC is the true target of the return instruction that we'll execute. */ 539 #if defined(CONFIG_TCG_INTERPRETER) 540 extern __thread uintptr_t tci_tb_ptr; 541 # define GETPC() tci_tb_ptr 542 #else 543 # define GETPC() \ 544 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) 545 #endif 546 547 /* The true return address will often point to a host insn that is part of 548 the next translated guest insn. Adjust the address backward to point to 549 the middle of the call insn. Subtracting one would do the job except for 550 several compressed mode architectures (arm, mips) which set the low bit 551 to indicate the compressed mode; subtracting two works around that. It 552 is also the case that there are no host isas that contain a call insn 553 smaller than 4 bytes, so we don't worry about special-casing this. */ 554 #define GETPC_ADJ 2 555 556 #if !defined(CONFIG_USER_ONLY) 557 558 /** 559 * iotlb_to_section: 560 * @cpu: CPU performing the access 561 * @index: TCG CPU IOTLB entry 562 * 563 * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that 564 * it refers to. @index will have been initially created and returned 565 * by memory_region_section_get_iotlb(). 566 */ 567 struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, 568 hwaddr index, MemTxAttrs attrs); 569 #endif 570 571 /** 572 * get_page_addr_code_hostp() 573 * @env: CPUArchState 574 * @addr: guest virtual address of guest code 575 * 576 * See get_page_addr_code() (full-system version) for documentation on the 577 * return value. 578 * 579 * Sets *@hostp (when @hostp is non-NULL) as follows. 580 * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp 581 * to the host address where @addr's content is kept. 582 * 583 * Note: this function can trigger an exception. 584 */ 585 tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr, 586 void **hostp); 587 588 /** 589 * get_page_addr_code() 590 * @env: CPUArchState 591 * @addr: guest virtual address of guest code 592 * 593 * If we cannot translate and execute from the entire RAM page, or if 594 * the region is not backed by RAM, returns -1. Otherwise, returns the 595 * ram_addr_t corresponding to the guest code at @addr. 596 * 597 * Note: this function can trigger an exception. 598 */ 599 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, 600 target_ulong addr) 601 { 602 return get_page_addr_code_hostp(env, addr, NULL); 603 } 604 605 #if defined(CONFIG_USER_ONLY) 606 void TSA_NO_TSA mmap_lock(void); 607 void TSA_NO_TSA mmap_unlock(void); 608 bool have_mmap_lock(void); 609 610 /** 611 * adjust_signal_pc: 612 * @pc: raw pc from the host signal ucontext_t. 613 * @is_write: host memory operation was write, or read-modify-write. 614 * 615 * Alter @pc as required for unwinding. Return the type of the 616 * guest memory access -- host reads may be for guest execution. 617 */ 618 MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); 619 620 /** 621 * handle_sigsegv_accerr_write: 622 * @cpu: the cpu context 623 * @old_set: the sigset_t from the signal ucontext_t 624 * @host_pc: the host pc, adjusted for the signal 625 * @host_addr: the host address of the fault 626 * 627 * Return true if the write fault has been handled, and should be re-tried. 628 */ 629 bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, 630 uintptr_t host_pc, abi_ptr guest_addr); 631 632 /** 633 * cpu_loop_exit_sigsegv: 634 * @cpu: the cpu context 635 * @addr: the guest address of the fault 636 * @access_type: access was read/write/execute 637 * @maperr: true for invalid page, false for permission fault 638 * @ra: host pc for unwinding 639 * 640 * Use the TCGCPUOps hook to record cpu state, do guest operating system 641 * specific things to raise SIGSEGV, and jump to the main cpu loop. 642 */ 643 G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, 644 MMUAccessType access_type, 645 bool maperr, uintptr_t ra); 646 647 /** 648 * cpu_loop_exit_sigbus: 649 * @cpu: the cpu context 650 * @addr: the guest address of the alignment fault 651 * @access_type: access was read/write/execute 652 * @ra: host pc for unwinding 653 * 654 * Use the TCGCPUOps hook to record cpu state, do guest operating system 655 * specific things to raise SIGBUS, and jump to the main cpu loop. 656 */ 657 G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, 658 MMUAccessType access_type, 659 uintptr_t ra); 660 661 #else 662 static inline void mmap_lock(void) {} 663 static inline void mmap_unlock(void) {} 664 665 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); 666 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr); 667 668 MemoryRegionSection * 669 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, 670 hwaddr *xlat, hwaddr *plen, 671 MemTxAttrs attrs, int *prot); 672 hwaddr memory_region_section_get_iotlb(CPUState *cpu, 673 MemoryRegionSection *section); 674 #endif 675 676 #endif 677