1 /* 2 * internal execution defines for qemu 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef _EXEC_ALL_H_ 21 #define _EXEC_ALL_H_ 22 23 #include "qemu-common.h" 24 25 /* allow to see translation results - the slowdown should be negligible, so we leave it */ 26 #define DEBUG_DISAS 27 28 /* Page tracking code uses ram addresses in system mode, and virtual 29 addresses in userspace mode. Define tb_page_addr_t to be an appropriate 30 type. */ 31 #if defined(CONFIG_USER_ONLY) 32 typedef abi_ulong tb_page_addr_t; 33 #else 34 typedef ram_addr_t tb_page_addr_t; 35 #endif 36 37 /* is_jmp field values */ 38 #define DISAS_NEXT 0 /* next instruction can be analyzed */ 39 #define DISAS_JUMP 1 /* only pc was modified dynamically */ 40 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ 41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */ 42 43 struct TranslationBlock; 44 typedef struct TranslationBlock TranslationBlock; 45 46 /* XXX: make safe guess about sizes */ 47 #define MAX_OP_PER_INSTR 208 48 49 #if HOST_LONG_BITS == 32 50 #define MAX_OPC_PARAM_PER_ARG 2 51 #else 52 #define MAX_OPC_PARAM_PER_ARG 1 53 #endif 54 #define MAX_OPC_PARAM_IARGS 5 55 #define MAX_OPC_PARAM_OARGS 1 56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) 57 58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs, 59 * and up to 4 + N parameters on 64-bit archs 60 * (N = number of input arguments + output arguments). */ 61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) 62 #define OPC_BUF_SIZE 640 63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) 64 65 /* Maximum size a TCG op can expand to. This is complicated because a 66 single op may require several host instructions and register reloads. 67 For now take a wild guess at 192 bytes, which should allow at least 68 a couple of fixup instructions per argument. */ 69 #define TCG_MAX_OP_SIZE 192 70 71 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) 72 73 #include "qemu/log.h" 74 75 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb); 76 void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb); 77 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, 78 int pc_pos); 79 80 void cpu_gen_init(void); 81 int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb, 82 int *gen_code_size_ptr); 83 bool cpu_restore_state(CPUArchState *env, uintptr_t searched_pc); 84 void page_size_init(void); 85 86 void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc); 87 void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr); 88 TranslationBlock *tb_gen_code(CPUArchState *env, 89 target_ulong pc, target_ulong cs_base, int flags, 90 int cflags); 91 void cpu_exec_init(CPUArchState *env); 92 void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1); 93 int page_unprotect(target_ulong address, uintptr_t pc, void *puc); 94 void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, 95 int is_cpu_write_access); 96 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end, 97 int is_cpu_write_access); 98 #if !defined(CONFIG_USER_ONLY) 99 /* cputlb.c */ 100 void tlb_flush_page(CPUArchState *env, target_ulong addr); 101 void tlb_flush(CPUArchState *env, int flush_global); 102 void tlb_set_page(CPUArchState *env, target_ulong vaddr, 103 hwaddr paddr, int prot, 104 int mmu_idx, target_ulong size); 105 void tb_invalidate_phys_addr(hwaddr addr); 106 #else 107 static inline void tlb_flush_page(CPUArchState *env, target_ulong addr) 108 { 109 } 110 111 static inline void tlb_flush(CPUArchState *env, int flush_global) 112 { 113 } 114 #endif 115 116 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ 117 118 #define CODE_GEN_PHYS_HASH_BITS 15 119 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) 120 121 /* estimated block size for TB allocation */ 122 /* XXX: use a per code average code fragment size and modulate it 123 according to the host CPU */ 124 #if defined(CONFIG_SOFTMMU) 125 #define CODE_GEN_AVG_BLOCK_SIZE 128 126 #else 127 #define CODE_GEN_AVG_BLOCK_SIZE 64 128 #endif 129 130 #if defined(__arm__) || defined(_ARCH_PPC) \ 131 || defined(__x86_64__) || defined(__i386__) \ 132 || defined(__sparc__) || defined(__aarch64__) \ 133 || defined(CONFIG_TCG_INTERPRETER) 134 #define USE_DIRECT_JUMP 135 #endif 136 137 struct TranslationBlock { 138 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ 139 target_ulong cs_base; /* CS base for this block */ 140 uint64_t flags; /* flags defining in which context the code was generated */ 141 uint16_t size; /* size of target code for this block (1 <= 142 size <= TARGET_PAGE_SIZE) */ 143 uint16_t cflags; /* compile flags */ 144 #define CF_COUNT_MASK 0x7fff 145 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ 146 147 uint8_t *tc_ptr; /* pointer to the translated code */ 148 /* next matching tb for physical address. */ 149 struct TranslationBlock *phys_hash_next; 150 /* first and second physical page containing code. The lower bit 151 of the pointer tells the index in page_next[] */ 152 struct TranslationBlock *page_next[2]; 153 tb_page_addr_t page_addr[2]; 154 155 /* the following data are used to directly call another TB from 156 the code of this one. */ 157 uint16_t tb_next_offset[2]; /* offset of original jump target */ 158 #ifdef USE_DIRECT_JUMP 159 uint16_t tb_jmp_offset[2]; /* offset of jump instruction */ 160 #else 161 uintptr_t tb_next[2]; /* address of jump generated code */ 162 #endif 163 /* list of TBs jumping to this one. This is a circular list using 164 the two least significant bits of the pointers to tell what is 165 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = 166 jmp_first */ 167 struct TranslationBlock *jmp_next[2]; 168 struct TranslationBlock *jmp_first; 169 uint32_t icount; 170 }; 171 172 #include "exec/spinlock.h" 173 174 typedef struct TBContext TBContext; 175 176 struct TBContext { 177 178 TranslationBlock *tbs; 179 TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; 180 int nb_tbs; 181 /* any access to the tbs or the page table must use this lock */ 182 spinlock_t tb_lock; 183 184 /* statistics */ 185 int tb_flush_count; 186 int tb_phys_invalidate_count; 187 188 int tb_invalidated_flag; 189 }; 190 191 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) 192 { 193 target_ulong tmp; 194 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); 195 return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK; 196 } 197 198 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) 199 { 200 target_ulong tmp; 201 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); 202 return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK) 203 | (tmp & TB_JMP_ADDR_MASK)); 204 } 205 206 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) 207 { 208 return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1); 209 } 210 211 void tb_free(TranslationBlock *tb); 212 void tb_flush(CPUArchState *env); 213 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); 214 215 #if defined(USE_DIRECT_JUMP) 216 217 #if defined(CONFIG_TCG_INTERPRETER) 218 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 219 { 220 /* patch the branch destination */ 221 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); 222 /* no need to flush icache explicitly */ 223 } 224 #elif defined(_ARCH_PPC) 225 void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr); 226 #define tb_set_jmp_target1 ppc_tb_set_jmp_target 227 #elif defined(__i386__) || defined(__x86_64__) 228 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 229 { 230 /* patch the branch destination */ 231 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); 232 /* no need to flush icache explicitly */ 233 } 234 #elif defined(__aarch64__) 235 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); 236 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target 237 #elif defined(__arm__) 238 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 239 { 240 #if !QEMU_GNUC_PREREQ(4, 1) 241 register unsigned long _beg __asm ("a1"); 242 register unsigned long _end __asm ("a2"); 243 register unsigned long _flg __asm ("a3"); 244 #endif 245 246 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ 247 *(uint32_t *)jmp_addr = 248 (*(uint32_t *)jmp_addr & ~0xffffff) 249 | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff); 250 251 #if QEMU_GNUC_PREREQ(4, 1) 252 __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); 253 #else 254 /* flush icache */ 255 _beg = jmp_addr; 256 _end = jmp_addr + 4; 257 _flg = 0; 258 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); 259 #endif 260 } 261 #elif defined(__sparc__) 262 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr); 263 #else 264 #error tb_set_jmp_target1 is missing 265 #endif 266 267 static inline void tb_set_jmp_target(TranslationBlock *tb, 268 int n, uintptr_t addr) 269 { 270 uint16_t offset = tb->tb_jmp_offset[n]; 271 tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); 272 } 273 274 #else 275 276 /* set the jump target */ 277 static inline void tb_set_jmp_target(TranslationBlock *tb, 278 int n, uintptr_t addr) 279 { 280 tb->tb_next[n] = addr; 281 } 282 283 #endif 284 285 static inline void tb_add_jump(TranslationBlock *tb, int n, 286 TranslationBlock *tb_next) 287 { 288 /* NOTE: this test is only needed for thread safety */ 289 if (!tb->jmp_next[n]) { 290 /* patch the native jump address */ 291 tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); 292 293 /* add in TB jmp circular list */ 294 tb->jmp_next[n] = tb_next->jmp_first; 295 tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n)); 296 } 297 } 298 299 /* GETRA is the true target of the return instruction that we'll execute, 300 defined here for simplicity of defining the follow-up macros. */ 301 #if defined(CONFIG_TCG_INTERPRETER) 302 extern uintptr_t tci_tb_ptr; 303 # define GETRA() tci_tb_ptr 304 #else 305 # define GETRA() \ 306 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) 307 #endif 308 309 /* The true return address will often point to a host insn that is part of 310 the next translated guest insn. Adjust the address backward to point to 311 the middle of the call insn. Subtracting one would do the job except for 312 several compressed mode architectures (arm, mips) which set the low bit 313 to indicate the compressed mode; subtracting two works around that. It 314 is also the case that there are no host isas that contain a call insn 315 smaller than 4 bytes, so we don't worry about special-casing this. */ 316 #if defined(CONFIG_TCG_INTERPRETER) 317 # define GETPC_ADJ 0 318 #else 319 # define GETPC_ADJ 2 320 #endif 321 322 #define GETPC() (GETRA() - GETPC_ADJ) 323 324 #if !defined(CONFIG_USER_ONLY) 325 326 void phys_mem_set_alloc(void *(*alloc)(size_t)); 327 328 struct MemoryRegion *iotlb_to_region(hwaddr index); 329 bool io_mem_read(struct MemoryRegion *mr, hwaddr addr, 330 uint64_t *pvalue, unsigned size); 331 bool io_mem_write(struct MemoryRegion *mr, hwaddr addr, 332 uint64_t value, unsigned size); 333 334 void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx, 335 uintptr_t retaddr); 336 337 uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); 338 uint16_t helper_ldw_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); 339 uint32_t helper_ldl_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); 340 uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx); 341 342 #define ACCESS_TYPE (NB_MMU_MODES + 1) 343 #define MEMSUFFIX _code 344 345 #define DATA_SIZE 1 346 #include "exec/softmmu_header.h" 347 348 #define DATA_SIZE 2 349 #include "exec/softmmu_header.h" 350 351 #define DATA_SIZE 4 352 #include "exec/softmmu_header.h" 353 354 #define DATA_SIZE 8 355 #include "exec/softmmu_header.h" 356 357 #undef ACCESS_TYPE 358 #undef MEMSUFFIX 359 360 #endif 361 362 #if defined(CONFIG_USER_ONLY) 363 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) 364 { 365 return addr; 366 } 367 #else 368 /* cputlb.c */ 369 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr); 370 #endif 371 372 typedef void (CPUDebugExcpHandler)(CPUArchState *env); 373 374 void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler); 375 376 /* vl.c */ 377 extern int singlestep; 378 379 /* cpu-exec.c */ 380 extern volatile sig_atomic_t exit_request; 381 382 /* Deterministic execution requires that IO only be performed on the last 383 instruction of a TB so that interrupts take effect immediately. */ 384 static inline int can_do_io(CPUArchState *env) 385 { 386 CPUState *cpu = ENV_GET_CPU(env); 387 388 if (!use_icount) { 389 return 1; 390 } 391 /* If not executing code then assume we are ok. */ 392 if (cpu->current_tb == NULL) { 393 return 1; 394 } 395 return env->can_do_io != 0; 396 } 397 398 #endif 399