1 /* 2 * internal execution defines for qemu 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef EXEC_ALL_H 21 #define EXEC_ALL_H 22 23 #include "qemu-common.h" 24 #include "exec/tb-context.h" 25 26 /* allow to see translation results - the slowdown should be negligible, so we leave it */ 27 #define DEBUG_DISAS 28 29 /* Page tracking code uses ram addresses in system mode, and virtual 30 addresses in userspace mode. Define tb_page_addr_t to be an appropriate 31 type. */ 32 #if defined(CONFIG_USER_ONLY) 33 typedef abi_ulong tb_page_addr_t; 34 #define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx 35 #else 36 typedef ram_addr_t tb_page_addr_t; 37 #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT 38 #endif 39 40 #include "qemu/log.h" 41 42 void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb); 43 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, 44 target_ulong *data); 45 46 void cpu_gen_init(void); 47 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); 48 49 void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu); 50 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); 51 TranslationBlock *tb_gen_code(CPUState *cpu, 52 target_ulong pc, target_ulong cs_base, 53 uint32_t flags, 54 int cflags); 55 56 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); 57 void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); 58 void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); 59 60 #if !defined(CONFIG_USER_ONLY) 61 void cpu_reloading_memory_map(void); 62 /** 63 * cpu_address_space_init: 64 * @cpu: CPU to add this address space to 65 * @as: address space to add 66 * @asidx: integer index of this address space 67 * 68 * Add the specified address space to the CPU's cpu_ases list. 69 * The address space added with @asidx 0 is the one used for the 70 * convenience pointer cpu->as. 71 * The target-specific code which registers ASes is responsible 72 * for defining what semantics address space 0, 1, 2, etc have. 73 * 74 * Before the first call to this function, the caller must set 75 * cpu->num_ases to the total number of address spaces it needs 76 * to support. 77 * 78 * Note that with KVM only one address space is supported. 79 */ 80 void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx); 81 #endif 82 83 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 84 /* cputlb.c */ 85 /** 86 * tlb_flush_page: 87 * @cpu: CPU whose TLB should be flushed 88 * @addr: virtual address of page to be flushed 89 * 90 * Flush one page from the TLB of the specified CPU, for all 91 * MMU indexes. 92 */ 93 void tlb_flush_page(CPUState *cpu, target_ulong addr); 94 /** 95 * tlb_flush_page_all_cpus: 96 * @cpu: src CPU of the flush 97 * @addr: virtual address of page to be flushed 98 * 99 * Flush one page from the TLB of the specified CPU, for all 100 * MMU indexes. 101 */ 102 void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr); 103 /** 104 * tlb_flush_page_all_cpus_synced: 105 * @cpu: src CPU of the flush 106 * @addr: virtual address of page to be flushed 107 * 108 * Flush one page from the TLB of the specified CPU, for all MMU 109 * indexes like tlb_flush_page_all_cpus except the source vCPUs work 110 * is scheduled as safe work meaning all flushes will be complete once 111 * the source vCPUs safe work is complete. This will depend on when 112 * the guests translation ends the TB. 113 */ 114 void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr); 115 /** 116 * tlb_flush: 117 * @cpu: CPU whose TLB should be flushed 118 * 119 * Flush the entire TLB for the specified CPU. Most CPU architectures 120 * allow the implementation to drop entries from the TLB at any time 121 * so this is generally safe. If more selective flushing is required 122 * use one of the other functions for efficiency. 123 */ 124 void tlb_flush(CPUState *cpu); 125 /** 126 * tlb_flush_all_cpus: 127 * @cpu: src CPU of the flush 128 */ 129 void tlb_flush_all_cpus(CPUState *src_cpu); 130 /** 131 * tlb_flush_all_cpus_synced: 132 * @cpu: src CPU of the flush 133 * 134 * Like tlb_flush_all_cpus except this except the source vCPUs work is 135 * scheduled as safe work meaning all flushes will be complete once 136 * the source vCPUs safe work is complete. This will depend on when 137 * the guests translation ends the TB. 138 */ 139 void tlb_flush_all_cpus_synced(CPUState *src_cpu); 140 /** 141 * tlb_flush_page_by_mmuidx: 142 * @cpu: CPU whose TLB should be flushed 143 * @addr: virtual address of page to be flushed 144 * @idxmap: bitmap of MMU indexes to flush 145 * 146 * Flush one page from the TLB of the specified CPU, for the specified 147 * MMU indexes. 148 */ 149 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, 150 uint16_t idxmap); 151 /** 152 * tlb_flush_page_by_mmuidx_all_cpus: 153 * @cpu: Originating CPU of the flush 154 * @addr: virtual address of page to be flushed 155 * @idxmap: bitmap of MMU indexes to flush 156 * 157 * Flush one page from the TLB of all CPUs, for the specified 158 * MMU indexes. 159 */ 160 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, 161 uint16_t idxmap); 162 /** 163 * tlb_flush_page_by_mmuidx_all_cpus_synced: 164 * @cpu: Originating CPU of the flush 165 * @addr: virtual address of page to be flushed 166 * @idxmap: bitmap of MMU indexes to flush 167 * 168 * Flush one page from the TLB of all CPUs, for the specified MMU 169 * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source 170 * vCPUs work is scheduled as safe work meaning all flushes will be 171 * complete once the source vCPUs safe work is complete. This will 172 * depend on when the guests translation ends the TB. 173 */ 174 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr, 175 uint16_t idxmap); 176 /** 177 * tlb_flush_by_mmuidx: 178 * @cpu: CPU whose TLB should be flushed 179 * @wait: If true ensure synchronisation by exiting the cpu_loop 180 * @idxmap: bitmap of MMU indexes to flush 181 * 182 * Flush all entries from the TLB of the specified CPU, for the specified 183 * MMU indexes. 184 */ 185 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); 186 /** 187 * tlb_flush_by_mmuidx_all_cpus: 188 * @cpu: Originating CPU of the flush 189 * @idxmap: bitmap of MMU indexes to flush 190 * 191 * Flush all entries from all TLBs of all CPUs, for the specified 192 * MMU indexes. 193 */ 194 void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap); 195 /** 196 * tlb_flush_by_mmuidx_all_cpus_synced: 197 * @cpu: Originating CPU of the flush 198 * @idxmap: bitmap of MMU indexes to flush 199 * 200 * Flush all entries from all TLBs of all CPUs, for the specified 201 * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source 202 * vCPUs work is scheduled as safe work meaning all flushes will be 203 * complete once the source vCPUs safe work is complete. This will 204 * depend on when the guests translation ends the TB. 205 */ 206 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); 207 /** 208 * tlb_set_page_with_attrs: 209 * @cpu: CPU to add this TLB entry for 210 * @vaddr: virtual address of page to add entry for 211 * @paddr: physical address of the page 212 * @attrs: memory transaction attributes 213 * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) 214 * @mmu_idx: MMU index to insert TLB entry for 215 * @size: size of the page in bytes 216 * 217 * Add an entry to this CPU's TLB (a mapping from virtual address 218 * @vaddr to physical address @paddr) with the specified memory 219 * transaction attributes. This is generally called by the target CPU 220 * specific code after it has been called through the tlb_fill() 221 * entry point and performed a successful page table walk to find 222 * the physical address and attributes for the virtual address 223 * which provoked the TLB miss. 224 * 225 * At most one entry for a given virtual address is permitted. Only a 226 * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only 227 * used by tlb_flush_page. 228 */ 229 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, 230 hwaddr paddr, MemTxAttrs attrs, 231 int prot, int mmu_idx, target_ulong size); 232 /* tlb_set_page: 233 * 234 * This function is equivalent to calling tlb_set_page_with_attrs() 235 * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided 236 * as a convenience for CPUs which don't use memory transaction attributes. 237 */ 238 void tlb_set_page(CPUState *cpu, target_ulong vaddr, 239 hwaddr paddr, int prot, 240 int mmu_idx, target_ulong size); 241 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); 242 void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, 243 uintptr_t retaddr); 244 #else 245 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) 246 { 247 } 248 static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) 249 { 250 } 251 static inline void tlb_flush_page_all_cpus_synced(CPUState *src, 252 target_ulong addr) 253 { 254 } 255 static inline void tlb_flush(CPUState *cpu) 256 { 257 } 258 static inline void tlb_flush_all_cpus(CPUState *src_cpu) 259 { 260 } 261 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) 262 { 263 } 264 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, 265 target_ulong addr, uint16_t idxmap) 266 { 267 } 268 269 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) 270 { 271 } 272 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, 273 target_ulong addr, 274 uint16_t idxmap) 275 { 276 } 277 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, 278 target_ulong addr, 279 uint16_t idxmap) 280 { 281 } 282 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap) 283 { 284 } 285 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, 286 uint16_t idxmap) 287 { 288 } 289 static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) 290 { 291 } 292 #endif 293 294 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ 295 296 /* Estimated block size for TB allocation. */ 297 /* ??? The following is based on a 2015 survey of x86_64 host output. 298 Better would seem to be some sort of dynamically sized TB array, 299 adapting to the block sizes actually being produced. */ 300 #if defined(CONFIG_SOFTMMU) 301 #define CODE_GEN_AVG_BLOCK_SIZE 400 302 #else 303 #define CODE_GEN_AVG_BLOCK_SIZE 150 304 #endif 305 306 /* 307 * Translation Cache-related fields of a TB. 308 */ 309 struct tb_tc { 310 void *ptr; /* pointer to the translated code */ 311 uint8_t *search; /* pointer to search data */ 312 }; 313 314 struct TranslationBlock { 315 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ 316 target_ulong cs_base; /* CS base for this block */ 317 uint32_t flags; /* flags defining in which context the code was generated */ 318 uint16_t size; /* size of target code for this block (1 <= 319 size <= TARGET_PAGE_SIZE) */ 320 uint16_t icount; 321 uint32_t cflags; /* compile flags */ 322 #define CF_COUNT_MASK 0x7fff 323 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ 324 #define CF_NOCACHE 0x10000 /* To be freed after execution */ 325 #define CF_USE_ICOUNT 0x20000 326 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ 327 #define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_lock */ 328 329 /* Per-vCPU dynamic tracing state used to generate this TB */ 330 uint32_t trace_vcpu_dstate; 331 332 struct tb_tc tc; 333 334 /* original tb when cflags has CF_NOCACHE */ 335 struct TranslationBlock *orig_tb; 336 /* first and second physical page containing code. The lower bit 337 of the pointer tells the index in page_next[] */ 338 struct TranslationBlock *page_next[2]; 339 tb_page_addr_t page_addr[2]; 340 341 /* The following data are used to directly call another TB from 342 * the code of this one. This can be done either by emitting direct or 343 * indirect native jump instructions. These jumps are reset so that the TB 344 * just continues its execution. The TB can be linked to another one by 345 * setting one of the jump targets (or patching the jump instruction). Only 346 * two of such jumps are supported. 347 */ 348 uint16_t jmp_reset_offset[2]; /* offset of original jump target */ 349 #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */ 350 uintptr_t jmp_target_arg[2]; /* target address or offset */ 351 352 /* Each TB has an associated circular list of TBs jumping to this one. 353 * jmp_list_first points to the first TB jumping to this one. 354 * jmp_list_next is used to point to the next TB in a list. 355 * Since each TB can have two jumps, it can participate in two lists. 356 * jmp_list_first and jmp_list_next are 4-byte aligned pointers to a 357 * TranslationBlock structure, but the two least significant bits of 358 * them are used to encode which data field of the pointed TB should 359 * be used to traverse the list further from that TB: 360 * 0 => jmp_list_next[0], 1 => jmp_list_next[1], 2 => jmp_list_first. 361 * In other words, 0/1 tells which jump is used in the pointed TB, 362 * and 2 means that this is a pointer back to the target TB of this list. 363 */ 364 uintptr_t jmp_list_next[2]; 365 uintptr_t jmp_list_first; 366 }; 367 368 void tb_free(TranslationBlock *tb); 369 void tb_flush(CPUState *cpu); 370 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); 371 TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, 372 target_ulong cs_base, uint32_t flags); 373 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); 374 375 /* GETPC is the true target of the return instruction that we'll execute. */ 376 #if defined(CONFIG_TCG_INTERPRETER) 377 extern uintptr_t tci_tb_ptr; 378 # define GETPC() tci_tb_ptr 379 #else 380 # define GETPC() \ 381 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) 382 #endif 383 384 /* The true return address will often point to a host insn that is part of 385 the next translated guest insn. Adjust the address backward to point to 386 the middle of the call insn. Subtracting one would do the job except for 387 several compressed mode architectures (arm, mips) which set the low bit 388 to indicate the compressed mode; subtracting two works around that. It 389 is also the case that there are no host isas that contain a call insn 390 smaller than 4 bytes, so we don't worry about special-casing this. */ 391 #define GETPC_ADJ 2 392 393 void tb_lock(void); 394 void tb_unlock(void); 395 void tb_lock_reset(void); 396 397 #if !defined(CONFIG_USER_ONLY) 398 399 struct MemoryRegion *iotlb_to_region(CPUState *cpu, 400 hwaddr index, MemTxAttrs attrs); 401 402 void tlb_fill(CPUState *cpu, target_ulong addr, MMUAccessType access_type, 403 int mmu_idx, uintptr_t retaddr); 404 405 #endif 406 407 #if defined(CONFIG_USER_ONLY) 408 void mmap_lock(void); 409 void mmap_unlock(void); 410 bool have_mmap_lock(void); 411 412 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) 413 { 414 return addr; 415 } 416 #else 417 static inline void mmap_lock(void) {} 418 static inline void mmap_unlock(void) {} 419 420 /* cputlb.c */ 421 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr); 422 423 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); 424 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr); 425 426 /* exec.c */ 427 void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr); 428 429 MemoryRegionSection * 430 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, 431 hwaddr *xlat, hwaddr *plen); 432 hwaddr memory_region_section_get_iotlb(CPUState *cpu, 433 MemoryRegionSection *section, 434 target_ulong vaddr, 435 hwaddr paddr, hwaddr xlat, 436 int prot, 437 target_ulong *address); 438 bool memory_region_is_unassigned(MemoryRegion *mr); 439 440 #endif 441 442 /* vl.c */ 443 extern int singlestep; 444 445 #endif 446