1 /* 2 * internal execution defines for qemu 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef EXEC_ALL_H 21 #define EXEC_ALL_H 22 23 #include "qemu-common.h" 24 #include "exec/tb-context.h" 25 26 /* allow to see translation results - the slowdown should be negligible, so we leave it */ 27 #define DEBUG_DISAS 28 29 /* Page tracking code uses ram addresses in system mode, and virtual 30 addresses in userspace mode. Define tb_page_addr_t to be an appropriate 31 type. */ 32 #if defined(CONFIG_USER_ONLY) 33 typedef abi_ulong tb_page_addr_t; 34 #else 35 typedef ram_addr_t tb_page_addr_t; 36 #endif 37 38 /* is_jmp field values */ 39 #define DISAS_NEXT 0 /* next instruction can be analyzed */ 40 #define DISAS_JUMP 1 /* only pc was modified dynamically */ 41 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ 42 #define DISAS_TB_JUMP 3 /* only pc was modified statically */ 43 44 #include "qemu/log.h" 45 46 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb); 47 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, 48 target_ulong *data); 49 50 void cpu_gen_init(void); 51 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); 52 53 void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu); 54 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); 55 TranslationBlock *tb_gen_code(CPUState *cpu, 56 target_ulong pc, target_ulong cs_base, 57 uint32_t flags, 58 int cflags); 59 60 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); 61 void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); 62 void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); 63 64 #if !defined(CONFIG_USER_ONLY) 65 void cpu_reloading_memory_map(void); 66 /** 67 * cpu_address_space_init: 68 * @cpu: CPU to add this address space to 69 * @as: address space to add 70 * @asidx: integer index of this address space 71 * 72 * Add the specified address space to the CPU's cpu_ases list. 73 * The address space added with @asidx 0 is the one used for the 74 * convenience pointer cpu->as. 75 * The target-specific code which registers ASes is responsible 76 * for defining what semantics address space 0, 1, 2, etc have. 77 * 78 * Before the first call to this function, the caller must set 79 * cpu->num_ases to the total number of address spaces it needs 80 * to support. 81 * 82 * Note that with KVM only one address space is supported. 83 */ 84 void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx); 85 #endif 86 87 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 88 /* cputlb.c */ 89 /** 90 * tlb_flush_page: 91 * @cpu: CPU whose TLB should be flushed 92 * @addr: virtual address of page to be flushed 93 * 94 * Flush one page from the TLB of the specified CPU, for all 95 * MMU indexes. 96 */ 97 void tlb_flush_page(CPUState *cpu, target_ulong addr); 98 /** 99 * tlb_flush_page_all_cpus: 100 * @cpu: src CPU of the flush 101 * @addr: virtual address of page to be flushed 102 * 103 * Flush one page from the TLB of the specified CPU, for all 104 * MMU indexes. 105 */ 106 void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr); 107 /** 108 * tlb_flush_page_all_cpus_synced: 109 * @cpu: src CPU of the flush 110 * @addr: virtual address of page to be flushed 111 * 112 * Flush one page from the TLB of the specified CPU, for all MMU 113 * indexes like tlb_flush_page_all_cpus except the source vCPUs work 114 * is scheduled as safe work meaning all flushes will be complete once 115 * the source vCPUs safe work is complete. This will depend on when 116 * the guests translation ends the TB. 117 */ 118 void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr); 119 /** 120 * tlb_flush: 121 * @cpu: CPU whose TLB should be flushed 122 * 123 * Flush the entire TLB for the specified CPU. Most CPU architectures 124 * allow the implementation to drop entries from the TLB at any time 125 * so this is generally safe. If more selective flushing is required 126 * use one of the other functions for efficiency. 127 */ 128 void tlb_flush(CPUState *cpu); 129 /** 130 * tlb_flush_all_cpus: 131 * @cpu: src CPU of the flush 132 */ 133 void tlb_flush_all_cpus(CPUState *src_cpu); 134 /** 135 * tlb_flush_all_cpus_synced: 136 * @cpu: src CPU of the flush 137 * 138 * Like tlb_flush_all_cpus except this except the source vCPUs work is 139 * scheduled as safe work meaning all flushes will be complete once 140 * the source vCPUs safe work is complete. This will depend on when 141 * the guests translation ends the TB. 142 */ 143 void tlb_flush_all_cpus_synced(CPUState *src_cpu); 144 /** 145 * tlb_flush_page_by_mmuidx: 146 * @cpu: CPU whose TLB should be flushed 147 * @addr: virtual address of page to be flushed 148 * @idxmap: bitmap of MMU indexes to flush 149 * 150 * Flush one page from the TLB of the specified CPU, for the specified 151 * MMU indexes. 152 */ 153 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, 154 uint16_t idxmap); 155 /** 156 * tlb_flush_page_by_mmuidx_all_cpus: 157 * @cpu: Originating CPU of the flush 158 * @addr: virtual address of page to be flushed 159 * @idxmap: bitmap of MMU indexes to flush 160 * 161 * Flush one page from the TLB of all CPUs, for the specified 162 * MMU indexes. 163 */ 164 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, 165 uint16_t idxmap); 166 /** 167 * tlb_flush_page_by_mmuidx_all_cpus_synced: 168 * @cpu: Originating CPU of the flush 169 * @addr: virtual address of page to be flushed 170 * @idxmap: bitmap of MMU indexes to flush 171 * 172 * Flush one page from the TLB of all CPUs, for the specified MMU 173 * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source 174 * vCPUs work is scheduled as safe work meaning all flushes will be 175 * complete once the source vCPUs safe work is complete. This will 176 * depend on when the guests translation ends the TB. 177 */ 178 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr, 179 uint16_t idxmap); 180 /** 181 * tlb_flush_by_mmuidx: 182 * @cpu: CPU whose TLB should be flushed 183 * @wait: If true ensure synchronisation by exiting the cpu_loop 184 * @idxmap: bitmap of MMU indexes to flush 185 * 186 * Flush all entries from the TLB of the specified CPU, for the specified 187 * MMU indexes. 188 */ 189 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); 190 /** 191 * tlb_flush_by_mmuidx_all_cpus: 192 * @cpu: Originating CPU of the flush 193 * @idxmap: bitmap of MMU indexes to flush 194 * 195 * Flush all entries from all TLBs of all CPUs, for the specified 196 * MMU indexes. 197 */ 198 void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap); 199 /** 200 * tlb_flush_by_mmuidx_all_cpus_synced: 201 * @cpu: Originating CPU of the flush 202 * @idxmap: bitmap of MMU indexes to flush 203 * 204 * Flush all entries from all TLBs of all CPUs, for the specified 205 * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source 206 * vCPUs work is scheduled as safe work meaning all flushes will be 207 * complete once the source vCPUs safe work is complete. This will 208 * depend on when the guests translation ends the TB. 209 */ 210 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); 211 /** 212 * tlb_set_page_with_attrs: 213 * @cpu: CPU to add this TLB entry for 214 * @vaddr: virtual address of page to add entry for 215 * @paddr: physical address of the page 216 * @attrs: memory transaction attributes 217 * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) 218 * @mmu_idx: MMU index to insert TLB entry for 219 * @size: size of the page in bytes 220 * 221 * Add an entry to this CPU's TLB (a mapping from virtual address 222 * @vaddr to physical address @paddr) with the specified memory 223 * transaction attributes. This is generally called by the target CPU 224 * specific code after it has been called through the tlb_fill() 225 * entry point and performed a successful page table walk to find 226 * the physical address and attributes for the virtual address 227 * which provoked the TLB miss. 228 * 229 * At most one entry for a given virtual address is permitted. Only a 230 * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only 231 * used by tlb_flush_page. 232 */ 233 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, 234 hwaddr paddr, MemTxAttrs attrs, 235 int prot, int mmu_idx, target_ulong size); 236 /* tlb_set_page: 237 * 238 * This function is equivalent to calling tlb_set_page_with_attrs() 239 * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided 240 * as a convenience for CPUs which don't use memory transaction attributes. 241 */ 242 void tlb_set_page(CPUState *cpu, target_ulong vaddr, 243 hwaddr paddr, int prot, 244 int mmu_idx, target_ulong size); 245 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); 246 void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, 247 uintptr_t retaddr); 248 #else 249 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) 250 { 251 } 252 static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) 253 { 254 } 255 static inline void tlb_flush_page_all_cpus_synced(CPUState *src, 256 target_ulong addr) 257 { 258 } 259 static inline void tlb_flush(CPUState *cpu) 260 { 261 } 262 static inline void tlb_flush_all_cpus(CPUState *src_cpu) 263 { 264 } 265 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) 266 { 267 } 268 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, 269 target_ulong addr, uint16_t idxmap) 270 { 271 } 272 273 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) 274 { 275 } 276 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, 277 target_ulong addr, 278 uint16_t idxmap) 279 { 280 } 281 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, 282 target_ulong addr, 283 uint16_t idxmap) 284 { 285 } 286 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap) 287 { 288 } 289 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, 290 uint16_t idxmap) 291 { 292 } 293 static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) 294 { 295 } 296 #endif 297 298 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ 299 300 /* Estimated block size for TB allocation. */ 301 /* ??? The following is based on a 2015 survey of x86_64 host output. 302 Better would seem to be some sort of dynamically sized TB array, 303 adapting to the block sizes actually being produced. */ 304 #if defined(CONFIG_SOFTMMU) 305 #define CODE_GEN_AVG_BLOCK_SIZE 400 306 #else 307 #define CODE_GEN_AVG_BLOCK_SIZE 150 308 #endif 309 310 #if defined(_ARCH_PPC) \ 311 || defined(__x86_64__) || defined(__i386__) \ 312 || defined(__sparc__) || defined(__aarch64__) \ 313 || defined(__s390x__) || defined(__mips__) \ 314 || defined(CONFIG_TCG_INTERPRETER) 315 /* NOTE: Direct jump patching must be atomic to be thread-safe. */ 316 #define USE_DIRECT_JUMP 317 #endif 318 319 struct TranslationBlock { 320 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ 321 target_ulong cs_base; /* CS base for this block */ 322 uint32_t flags; /* flags defining in which context the code was generated */ 323 uint16_t size; /* size of target code for this block (1 <= 324 size <= TARGET_PAGE_SIZE) */ 325 uint16_t icount; 326 uint32_t cflags; /* compile flags */ 327 #define CF_COUNT_MASK 0x7fff 328 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ 329 #define CF_NOCACHE 0x10000 /* To be freed after execution */ 330 #define CF_USE_ICOUNT 0x20000 331 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ 332 333 /* Per-vCPU dynamic tracing state used to generate this TB */ 334 uint32_t trace_vcpu_dstate; 335 336 uint16_t invalid; 337 338 void *tc_ptr; /* pointer to the translated code */ 339 uint8_t *tc_search; /* pointer to search data */ 340 /* original tb when cflags has CF_NOCACHE */ 341 struct TranslationBlock *orig_tb; 342 /* first and second physical page containing code. The lower bit 343 of the pointer tells the index in page_next[] */ 344 struct TranslationBlock *page_next[2]; 345 tb_page_addr_t page_addr[2]; 346 347 /* The following data are used to directly call another TB from 348 * the code of this one. This can be done either by emitting direct or 349 * indirect native jump instructions. These jumps are reset so that the TB 350 * just continue its execution. The TB can be linked to another one by 351 * setting one of the jump targets (or patching the jump instruction). Only 352 * two of such jumps are supported. 353 */ 354 uint16_t jmp_reset_offset[2]; /* offset of original jump target */ 355 #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */ 356 #ifdef USE_DIRECT_JUMP 357 uint16_t jmp_insn_offset[2]; /* offset of native jump instruction */ 358 #else 359 uintptr_t jmp_target_addr[2]; /* target address for indirect jump */ 360 #endif 361 /* Each TB has an assosiated circular list of TBs jumping to this one. 362 * jmp_list_first points to the first TB jumping to this one. 363 * jmp_list_next is used to point to the next TB in a list. 364 * Since each TB can have two jumps, it can participate in two lists. 365 * jmp_list_first and jmp_list_next are 4-byte aligned pointers to a 366 * TranslationBlock structure, but the two least significant bits of 367 * them are used to encode which data field of the pointed TB should 368 * be used to traverse the list further from that TB: 369 * 0 => jmp_list_next[0], 1 => jmp_list_next[1], 2 => jmp_list_first. 370 * In other words, 0/1 tells which jump is used in the pointed TB, 371 * and 2 means that this is a pointer back to the target TB of this list. 372 */ 373 uintptr_t jmp_list_next[2]; 374 uintptr_t jmp_list_first; 375 }; 376 377 void tb_free(TranslationBlock *tb); 378 void tb_flush(CPUState *cpu); 379 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); 380 TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, 381 target_ulong cs_base, uint32_t flags); 382 383 #if defined(USE_DIRECT_JUMP) 384 385 #if defined(CONFIG_TCG_INTERPRETER) 386 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 387 { 388 /* patch the branch destination */ 389 atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); 390 /* no need to flush icache explicitly */ 391 } 392 #elif defined(_ARCH_PPC) 393 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); 394 #define tb_set_jmp_target1 ppc_tb_set_jmp_target 395 #elif defined(__i386__) || defined(__x86_64__) 396 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 397 { 398 /* patch the branch destination */ 399 atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); 400 /* no need to flush icache explicitly */ 401 } 402 #elif defined(__s390x__) 403 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 404 { 405 /* patch the branch destination */ 406 intptr_t disp = addr - (jmp_addr - 2); 407 atomic_set((int32_t *)jmp_addr, disp / 2); 408 /* no need to flush icache explicitly */ 409 } 410 #elif defined(__aarch64__) 411 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); 412 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target 413 #elif defined(__sparc__) || defined(__mips__) 414 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr); 415 #else 416 #error tb_set_jmp_target1 is missing 417 #endif 418 419 static inline void tb_set_jmp_target(TranslationBlock *tb, 420 int n, uintptr_t addr) 421 { 422 uint16_t offset = tb->jmp_insn_offset[n]; 423 tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); 424 } 425 426 #else 427 428 /* set the jump target */ 429 static inline void tb_set_jmp_target(TranslationBlock *tb, 430 int n, uintptr_t addr) 431 { 432 tb->jmp_target_addr[n] = addr; 433 } 434 435 #endif 436 437 /* Called with tb_lock held. */ 438 static inline void tb_add_jump(TranslationBlock *tb, int n, 439 TranslationBlock *tb_next) 440 { 441 assert(n < ARRAY_SIZE(tb->jmp_list_next)); 442 if (tb->jmp_list_next[n]) { 443 /* Another thread has already done this while we were 444 * outside of the lock; nothing to do in this case */ 445 return; 446 } 447 qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, 448 "Linking TBs %p [" TARGET_FMT_lx 449 "] index %d -> %p [" TARGET_FMT_lx "]\n", 450 tb->tc_ptr, tb->pc, n, 451 tb_next->tc_ptr, tb_next->pc); 452 453 /* patch the native jump address */ 454 tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); 455 456 /* add in TB jmp circular list */ 457 tb->jmp_list_next[n] = tb_next->jmp_list_first; 458 tb_next->jmp_list_first = (uintptr_t)tb | n; 459 } 460 461 /* GETPC is the true target of the return instruction that we'll execute. */ 462 #if defined(CONFIG_TCG_INTERPRETER) 463 extern uintptr_t tci_tb_ptr; 464 # define GETPC() tci_tb_ptr 465 #else 466 # define GETPC() \ 467 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) 468 #endif 469 470 /* The true return address will often point to a host insn that is part of 471 the next translated guest insn. Adjust the address backward to point to 472 the middle of the call insn. Subtracting one would do the job except for 473 several compressed mode architectures (arm, mips) which set the low bit 474 to indicate the compressed mode; subtracting two works around that. It 475 is also the case that there are no host isas that contain a call insn 476 smaller than 4 bytes, so we don't worry about special-casing this. */ 477 #define GETPC_ADJ 2 478 479 void tb_lock(void); 480 void tb_unlock(void); 481 void tb_lock_reset(void); 482 483 #if !defined(CONFIG_USER_ONLY) 484 485 struct MemoryRegion *iotlb_to_region(CPUState *cpu, 486 hwaddr index, MemTxAttrs attrs); 487 488 void tlb_fill(CPUState *cpu, target_ulong addr, MMUAccessType access_type, 489 int mmu_idx, uintptr_t retaddr); 490 491 #endif 492 493 #if defined(CONFIG_USER_ONLY) 494 void mmap_lock(void); 495 void mmap_unlock(void); 496 bool have_mmap_lock(void); 497 498 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) 499 { 500 return addr; 501 } 502 #else 503 static inline void mmap_lock(void) {} 504 static inline void mmap_unlock(void) {} 505 506 /* cputlb.c */ 507 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr); 508 509 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); 510 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr); 511 512 /* exec.c */ 513 void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr); 514 515 MemoryRegionSection * 516 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, 517 hwaddr *xlat, hwaddr *plen); 518 hwaddr memory_region_section_get_iotlb(CPUState *cpu, 519 MemoryRegionSection *section, 520 target_ulong vaddr, 521 hwaddr paddr, hwaddr xlat, 522 int prot, 523 target_ulong *address); 524 bool memory_region_is_unassigned(MemoryRegion *mr); 525 526 #endif 527 528 /* vl.c */ 529 extern int singlestep; 530 531 #endif 532