1 /* 2 * internal execution defines for qemu 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef EXEC_ALL_H 21 #define EXEC_ALL_H 22 23 #include "qemu-common.h" 24 #include "exec/tb-context.h" 25 #include "sysemu/cpus.h" 26 27 /* allow to see translation results - the slowdown should be negligible, so we leave it */ 28 #define DEBUG_DISAS 29 30 /* Page tracking code uses ram addresses in system mode, and virtual 31 addresses in userspace mode. Define tb_page_addr_t to be an appropriate 32 type. */ 33 #if defined(CONFIG_USER_ONLY) 34 typedef abi_ulong tb_page_addr_t; 35 #define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx 36 #else 37 typedef ram_addr_t tb_page_addr_t; 38 #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT 39 #endif 40 41 #include "qemu/log.h" 42 43 void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb); 44 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, 45 target_ulong *data); 46 47 void cpu_gen_init(void); 48 49 /** 50 * cpu_restore_state: 51 * @cpu: the vCPU state is to be restore to 52 * @searched_pc: the host PC the fault occurred at 53 * @return: true if state was restored, false otherwise 54 * 55 * Attempt to restore the state for a fault occurring in translated 56 * code. If the searched_pc is not in translated code no state is 57 * restored and the function returns false. 58 */ 59 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); 60 61 void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu); 62 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); 63 TranslationBlock *tb_gen_code(CPUState *cpu, 64 target_ulong pc, target_ulong cs_base, 65 uint32_t flags, 66 int cflags); 67 68 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); 69 void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); 70 void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); 71 72 #if !defined(CONFIG_USER_ONLY) 73 void cpu_reloading_memory_map(void); 74 /** 75 * cpu_address_space_init: 76 * @cpu: CPU to add this address space to 77 * @asidx: integer index of this address space 78 * @prefix: prefix to be used as name of address space 79 * @mr: the root memory region of address space 80 * 81 * Add the specified address space to the CPU's cpu_ases list. 82 * The address space added with @asidx 0 is the one used for the 83 * convenience pointer cpu->as. 84 * The target-specific code which registers ASes is responsible 85 * for defining what semantics address space 0, 1, 2, etc have. 86 * 87 * Before the first call to this function, the caller must set 88 * cpu->num_ases to the total number of address spaces it needs 89 * to support. 90 * 91 * Note that with KVM only one address space is supported. 92 */ 93 void cpu_address_space_init(CPUState *cpu, int asidx, 94 const char *prefix, MemoryRegion *mr); 95 #endif 96 97 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 98 /* cputlb.c */ 99 /** 100 * tlb_flush_page: 101 * @cpu: CPU whose TLB should be flushed 102 * @addr: virtual address of page to be flushed 103 * 104 * Flush one page from the TLB of the specified CPU, for all 105 * MMU indexes. 106 */ 107 void tlb_flush_page(CPUState *cpu, target_ulong addr); 108 /** 109 * tlb_flush_page_all_cpus: 110 * @cpu: src CPU of the flush 111 * @addr: virtual address of page to be flushed 112 * 113 * Flush one page from the TLB of the specified CPU, for all 114 * MMU indexes. 115 */ 116 void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr); 117 /** 118 * tlb_flush_page_all_cpus_synced: 119 * @cpu: src CPU of the flush 120 * @addr: virtual address of page to be flushed 121 * 122 * Flush one page from the TLB of the specified CPU, for all MMU 123 * indexes like tlb_flush_page_all_cpus except the source vCPUs work 124 * is scheduled as safe work meaning all flushes will be complete once 125 * the source vCPUs safe work is complete. This will depend on when 126 * the guests translation ends the TB. 127 */ 128 void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr); 129 /** 130 * tlb_flush: 131 * @cpu: CPU whose TLB should be flushed 132 * 133 * Flush the entire TLB for the specified CPU. Most CPU architectures 134 * allow the implementation to drop entries from the TLB at any time 135 * so this is generally safe. If more selective flushing is required 136 * use one of the other functions for efficiency. 137 */ 138 void tlb_flush(CPUState *cpu); 139 /** 140 * tlb_flush_all_cpus: 141 * @cpu: src CPU of the flush 142 */ 143 void tlb_flush_all_cpus(CPUState *src_cpu); 144 /** 145 * tlb_flush_all_cpus_synced: 146 * @cpu: src CPU of the flush 147 * 148 * Like tlb_flush_all_cpus except this except the source vCPUs work is 149 * scheduled as safe work meaning all flushes will be complete once 150 * the source vCPUs safe work is complete. This will depend on when 151 * the guests translation ends the TB. 152 */ 153 void tlb_flush_all_cpus_synced(CPUState *src_cpu); 154 /** 155 * tlb_flush_page_by_mmuidx: 156 * @cpu: CPU whose TLB should be flushed 157 * @addr: virtual address of page to be flushed 158 * @idxmap: bitmap of MMU indexes to flush 159 * 160 * Flush one page from the TLB of the specified CPU, for the specified 161 * MMU indexes. 162 */ 163 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, 164 uint16_t idxmap); 165 /** 166 * tlb_flush_page_by_mmuidx_all_cpus: 167 * @cpu: Originating CPU of the flush 168 * @addr: virtual address of page to be flushed 169 * @idxmap: bitmap of MMU indexes to flush 170 * 171 * Flush one page from the TLB of all CPUs, for the specified 172 * MMU indexes. 173 */ 174 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, 175 uint16_t idxmap); 176 /** 177 * tlb_flush_page_by_mmuidx_all_cpus_synced: 178 * @cpu: Originating CPU of the flush 179 * @addr: virtual address of page to be flushed 180 * @idxmap: bitmap of MMU indexes to flush 181 * 182 * Flush one page from the TLB of all CPUs, for the specified MMU 183 * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source 184 * vCPUs work is scheduled as safe work meaning all flushes will be 185 * complete once the source vCPUs safe work is complete. This will 186 * depend on when the guests translation ends the TB. 187 */ 188 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr, 189 uint16_t idxmap); 190 /** 191 * tlb_flush_by_mmuidx: 192 * @cpu: CPU whose TLB should be flushed 193 * @wait: If true ensure synchronisation by exiting the cpu_loop 194 * @idxmap: bitmap of MMU indexes to flush 195 * 196 * Flush all entries from the TLB of the specified CPU, for the specified 197 * MMU indexes. 198 */ 199 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); 200 /** 201 * tlb_flush_by_mmuidx_all_cpus: 202 * @cpu: Originating CPU of the flush 203 * @idxmap: bitmap of MMU indexes to flush 204 * 205 * Flush all entries from all TLBs of all CPUs, for the specified 206 * MMU indexes. 207 */ 208 void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap); 209 /** 210 * tlb_flush_by_mmuidx_all_cpus_synced: 211 * @cpu: Originating CPU of the flush 212 * @idxmap: bitmap of MMU indexes to flush 213 * 214 * Flush all entries from all TLBs of all CPUs, for the specified 215 * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source 216 * vCPUs work is scheduled as safe work meaning all flushes will be 217 * complete once the source vCPUs safe work is complete. This will 218 * depend on when the guests translation ends the TB. 219 */ 220 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); 221 /** 222 * tlb_set_page_with_attrs: 223 * @cpu: CPU to add this TLB entry for 224 * @vaddr: virtual address of page to add entry for 225 * @paddr: physical address of the page 226 * @attrs: memory transaction attributes 227 * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) 228 * @mmu_idx: MMU index to insert TLB entry for 229 * @size: size of the page in bytes 230 * 231 * Add an entry to this CPU's TLB (a mapping from virtual address 232 * @vaddr to physical address @paddr) with the specified memory 233 * transaction attributes. This is generally called by the target CPU 234 * specific code after it has been called through the tlb_fill() 235 * entry point and performed a successful page table walk to find 236 * the physical address and attributes for the virtual address 237 * which provoked the TLB miss. 238 * 239 * At most one entry for a given virtual address is permitted. Only a 240 * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only 241 * used by tlb_flush_page. 242 */ 243 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, 244 hwaddr paddr, MemTxAttrs attrs, 245 int prot, int mmu_idx, target_ulong size); 246 /* tlb_set_page: 247 * 248 * This function is equivalent to calling tlb_set_page_with_attrs() 249 * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided 250 * as a convenience for CPUs which don't use memory transaction attributes. 251 */ 252 void tlb_set_page(CPUState *cpu, target_ulong vaddr, 253 hwaddr paddr, int prot, 254 int mmu_idx, target_ulong size); 255 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); 256 void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, 257 uintptr_t retaddr); 258 #else 259 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) 260 { 261 } 262 static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) 263 { 264 } 265 static inline void tlb_flush_page_all_cpus_synced(CPUState *src, 266 target_ulong addr) 267 { 268 } 269 static inline void tlb_flush(CPUState *cpu) 270 { 271 } 272 static inline void tlb_flush_all_cpus(CPUState *src_cpu) 273 { 274 } 275 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) 276 { 277 } 278 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, 279 target_ulong addr, uint16_t idxmap) 280 { 281 } 282 283 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) 284 { 285 } 286 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, 287 target_ulong addr, 288 uint16_t idxmap) 289 { 290 } 291 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, 292 target_ulong addr, 293 uint16_t idxmap) 294 { 295 } 296 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap) 297 { 298 } 299 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, 300 uint16_t idxmap) 301 { 302 } 303 static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) 304 { 305 } 306 #endif 307 308 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ 309 310 /* Estimated block size for TB allocation. */ 311 /* ??? The following is based on a 2015 survey of x86_64 host output. 312 Better would seem to be some sort of dynamically sized TB array, 313 adapting to the block sizes actually being produced. */ 314 #if defined(CONFIG_SOFTMMU) 315 #define CODE_GEN_AVG_BLOCK_SIZE 400 316 #else 317 #define CODE_GEN_AVG_BLOCK_SIZE 150 318 #endif 319 320 /* 321 * Translation Cache-related fields of a TB. 322 * This struct exists just for convenience; we keep track of TB's in a binary 323 * search tree, and the only fields needed to compare TB's in the tree are 324 * @ptr and @size. 325 * Note: the address of search data can be obtained by adding @size to @ptr. 326 */ 327 struct tb_tc { 328 void *ptr; /* pointer to the translated code */ 329 size_t size; 330 }; 331 332 struct TranslationBlock { 333 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ 334 target_ulong cs_base; /* CS base for this block */ 335 uint32_t flags; /* flags defining in which context the code was generated */ 336 uint16_t size; /* size of target code for this block (1 <= 337 size <= TARGET_PAGE_SIZE) */ 338 uint16_t icount; 339 uint32_t cflags; /* compile flags */ 340 #define CF_COUNT_MASK 0x00007fff 341 #define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ 342 #define CF_NOCACHE 0x00010000 /* To be freed after execution */ 343 #define CF_USE_ICOUNT 0x00020000 344 #define CF_INVALID 0x00040000 /* TB is stale. Setters need tb_lock */ 345 #define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ 346 /* cflags' mask for hashing/comparison */ 347 #define CF_HASH_MASK \ 348 (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL) 349 350 /* Per-vCPU dynamic tracing state used to generate this TB */ 351 uint32_t trace_vcpu_dstate; 352 353 struct tb_tc tc; 354 355 /* original tb when cflags has CF_NOCACHE */ 356 struct TranslationBlock *orig_tb; 357 /* first and second physical page containing code. The lower bit 358 of the pointer tells the index in page_next[] */ 359 struct TranslationBlock *page_next[2]; 360 tb_page_addr_t page_addr[2]; 361 362 /* The following data are used to directly call another TB from 363 * the code of this one. This can be done either by emitting direct or 364 * indirect native jump instructions. These jumps are reset so that the TB 365 * just continues its execution. The TB can be linked to another one by 366 * setting one of the jump targets (or patching the jump instruction). Only 367 * two of such jumps are supported. 368 */ 369 uint16_t jmp_reset_offset[2]; /* offset of original jump target */ 370 #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */ 371 uintptr_t jmp_target_arg[2]; /* target address or offset */ 372 373 /* Each TB has an associated circular list of TBs jumping to this one. 374 * jmp_list_first points to the first TB jumping to this one. 375 * jmp_list_next is used to point to the next TB in a list. 376 * Since each TB can have two jumps, it can participate in two lists. 377 * jmp_list_first and jmp_list_next are 4-byte aligned pointers to a 378 * TranslationBlock structure, but the two least significant bits of 379 * them are used to encode which data field of the pointed TB should 380 * be used to traverse the list further from that TB: 381 * 0 => jmp_list_next[0], 1 => jmp_list_next[1], 2 => jmp_list_first. 382 * In other words, 0/1 tells which jump is used in the pointed TB, 383 * and 2 means that this is a pointer back to the target TB of this list. 384 */ 385 uintptr_t jmp_list_next[2]; 386 uintptr_t jmp_list_first; 387 }; 388 389 extern bool parallel_cpus; 390 391 /* Hide the atomic_read to make code a little easier on the eyes */ 392 static inline uint32_t tb_cflags(const TranslationBlock *tb) 393 { 394 return atomic_read(&tb->cflags); 395 } 396 397 /* current cflags for hashing/comparison */ 398 static inline uint32_t curr_cflags(void) 399 { 400 return (parallel_cpus ? CF_PARALLEL : 0) 401 | (use_icount ? CF_USE_ICOUNT : 0); 402 } 403 404 void tb_remove(TranslationBlock *tb); 405 void tb_flush(CPUState *cpu); 406 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); 407 TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, 408 target_ulong cs_base, uint32_t flags, 409 uint32_t cf_mask); 410 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); 411 412 /* GETPC is the true target of the return instruction that we'll execute. */ 413 #if defined(CONFIG_TCG_INTERPRETER) 414 extern uintptr_t tci_tb_ptr; 415 # define GETPC() tci_tb_ptr 416 #else 417 # define GETPC() \ 418 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) 419 #endif 420 421 /* The true return address will often point to a host insn that is part of 422 the next translated guest insn. Adjust the address backward to point to 423 the middle of the call insn. Subtracting one would do the job except for 424 several compressed mode architectures (arm, mips) which set the low bit 425 to indicate the compressed mode; subtracting two works around that. It 426 is also the case that there are no host isas that contain a call insn 427 smaller than 4 bytes, so we don't worry about special-casing this. */ 428 #define GETPC_ADJ 2 429 430 void tb_lock(void); 431 void tb_unlock(void); 432 void tb_lock_reset(void); 433 434 #if !defined(CONFIG_USER_ONLY) 435 436 struct MemoryRegion *iotlb_to_region(CPUState *cpu, 437 hwaddr index, MemTxAttrs attrs); 438 439 void tlb_fill(CPUState *cpu, target_ulong addr, MMUAccessType access_type, 440 int mmu_idx, uintptr_t retaddr); 441 442 #endif 443 444 #if defined(CONFIG_USER_ONLY) 445 void mmap_lock(void); 446 void mmap_unlock(void); 447 bool have_mmap_lock(void); 448 449 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) 450 { 451 return addr; 452 } 453 #else 454 static inline void mmap_lock(void) {} 455 static inline void mmap_unlock(void) {} 456 457 /* cputlb.c */ 458 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr); 459 460 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); 461 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr); 462 463 /* exec.c */ 464 void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr); 465 466 MemoryRegionSection * 467 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, 468 hwaddr *xlat, hwaddr *plen); 469 hwaddr memory_region_section_get_iotlb(CPUState *cpu, 470 MemoryRegionSection *section, 471 target_ulong vaddr, 472 hwaddr paddr, hwaddr xlat, 473 int prot, 474 target_ulong *address); 475 bool memory_region_is_unassigned(MemoryRegion *mr); 476 477 #endif 478 479 /* vl.c */ 480 extern int singlestep; 481 482 #endif 483