1 /* 2 * internal execution defines for qemu 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef EXEC_ALL_H 21 #define EXEC_ALL_H 22 23 #include "cpu.h" 24 #if defined(CONFIG_USER_ONLY) 25 #include "exec/cpu_ldst.h" 26 #endif 27 #include "exec/translation-block.h" 28 #include "qemu/clang-tsa.h" 29 30 /** 31 * cpu_unwind_state_data: 32 * @cpu: the cpu context 33 * @host_pc: the host pc within the translation 34 * @data: output data 35 * 36 * Attempt to load the the unwind state for a host pc occurring in 37 * translated code. If @host_pc is not in translated code, the 38 * function returns false; otherwise @data is loaded. 39 * This is the same unwind info as given to restore_state_to_opc. 40 */ 41 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); 42 43 /** 44 * cpu_restore_state: 45 * @cpu: the cpu context 46 * @host_pc: the host pc within the translation 47 * @return: true if state was restored, false otherwise 48 * 49 * Attempt to restore the state for a fault occurring in translated 50 * code. If @host_pc is not in translated code no state is 51 * restored and the function returns false. 52 */ 53 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); 54 55 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); 56 G_NORETURN void cpu_loop_exit(CPUState *cpu); 57 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); 58 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); 59 60 /** 61 * cpu_loop_exit_requested: 62 * @cpu: The CPU state to be tested 63 * 64 * Indicate if somebody asked for a return of the CPU to the main loop 65 * (e.g., via cpu_exit() or cpu_interrupt()). 66 * 67 * This is helpful for architectures that support interruptible 68 * instructions. After writing back all state to registers/memory, this 69 * call can be used to check if it makes sense to return to the main loop 70 * or to continue executing the interruptible instruction. 71 */ 72 static inline bool cpu_loop_exit_requested(CPUState *cpu) 73 { 74 return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0; 75 } 76 77 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 78 /* cputlb.c */ 79 /** 80 * tlb_init - initialize a CPU's TLB 81 * @cpu: CPU whose TLB should be initialized 82 */ 83 void tlb_init(CPUState *cpu); 84 /** 85 * tlb_destroy - destroy a CPU's TLB 86 * @cpu: CPU whose TLB should be destroyed 87 */ 88 void tlb_destroy(CPUState *cpu); 89 /** 90 * tlb_flush_page: 91 * @cpu: CPU whose TLB should be flushed 92 * @addr: virtual address of page to be flushed 93 * 94 * Flush one page from the TLB of the specified CPU, for all 95 * MMU indexes. 96 */ 97 void tlb_flush_page(CPUState *cpu, vaddr addr); 98 /** 99 * tlb_flush_page_all_cpus: 100 * @cpu: src CPU of the flush 101 * @addr: virtual address of page to be flushed 102 * 103 * Flush one page from the TLB of the specified CPU, for all 104 * MMU indexes. 105 */ 106 void tlb_flush_page_all_cpus(CPUState *src, vaddr addr); 107 /** 108 * tlb_flush_page_all_cpus_synced: 109 * @cpu: src CPU of the flush 110 * @addr: virtual address of page to be flushed 111 * 112 * Flush one page from the TLB of the specified CPU, for all MMU 113 * indexes like tlb_flush_page_all_cpus except the source vCPUs work 114 * is scheduled as safe work meaning all flushes will be complete once 115 * the source vCPUs safe work is complete. This will depend on when 116 * the guests translation ends the TB. 117 */ 118 void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); 119 /** 120 * tlb_flush: 121 * @cpu: CPU whose TLB should be flushed 122 * 123 * Flush the entire TLB for the specified CPU. Most CPU architectures 124 * allow the implementation to drop entries from the TLB at any time 125 * so this is generally safe. If more selective flushing is required 126 * use one of the other functions for efficiency. 127 */ 128 void tlb_flush(CPUState *cpu); 129 /** 130 * tlb_flush_all_cpus: 131 * @cpu: src CPU of the flush 132 */ 133 void tlb_flush_all_cpus(CPUState *src_cpu); 134 /** 135 * tlb_flush_all_cpus_synced: 136 * @cpu: src CPU of the flush 137 * 138 * Like tlb_flush_all_cpus except this except the source vCPUs work is 139 * scheduled as safe work meaning all flushes will be complete once 140 * the source vCPUs safe work is complete. This will depend on when 141 * the guests translation ends the TB. 142 */ 143 void tlb_flush_all_cpus_synced(CPUState *src_cpu); 144 /** 145 * tlb_flush_page_by_mmuidx: 146 * @cpu: CPU whose TLB should be flushed 147 * @addr: virtual address of page to be flushed 148 * @idxmap: bitmap of MMU indexes to flush 149 * 150 * Flush one page from the TLB of the specified CPU, for the specified 151 * MMU indexes. 152 */ 153 void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, 154 uint16_t idxmap); 155 /** 156 * tlb_flush_page_by_mmuidx_all_cpus: 157 * @cpu: Originating CPU of the flush 158 * @addr: virtual address of page to be flushed 159 * @idxmap: bitmap of MMU indexes to flush 160 * 161 * Flush one page from the TLB of all CPUs, for the specified 162 * MMU indexes. 163 */ 164 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr, 165 uint16_t idxmap); 166 /** 167 * tlb_flush_page_by_mmuidx_all_cpus_synced: 168 * @cpu: Originating CPU of the flush 169 * @addr: virtual address of page to be flushed 170 * @idxmap: bitmap of MMU indexes to flush 171 * 172 * Flush one page from the TLB of all CPUs, for the specified MMU 173 * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source 174 * vCPUs work is scheduled as safe work meaning all flushes will be 175 * complete once the source vCPUs safe work is complete. This will 176 * depend on when the guests translation ends the TB. 177 */ 178 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, 179 uint16_t idxmap); 180 /** 181 * tlb_flush_by_mmuidx: 182 * @cpu: CPU whose TLB should be flushed 183 * @wait: If true ensure synchronisation by exiting the cpu_loop 184 * @idxmap: bitmap of MMU indexes to flush 185 * 186 * Flush all entries from the TLB of the specified CPU, for the specified 187 * MMU indexes. 188 */ 189 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); 190 /** 191 * tlb_flush_by_mmuidx_all_cpus: 192 * @cpu: Originating CPU of the flush 193 * @idxmap: bitmap of MMU indexes to flush 194 * 195 * Flush all entries from all TLBs of all CPUs, for the specified 196 * MMU indexes. 197 */ 198 void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap); 199 /** 200 * tlb_flush_by_mmuidx_all_cpus_synced: 201 * @cpu: Originating CPU of the flush 202 * @idxmap: bitmap of MMU indexes to flush 203 * 204 * Flush all entries from all TLBs of all CPUs, for the specified 205 * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source 206 * vCPUs work is scheduled as safe work meaning all flushes will be 207 * complete once the source vCPUs safe work is complete. This will 208 * depend on when the guests translation ends the TB. 209 */ 210 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); 211 212 /** 213 * tlb_flush_page_bits_by_mmuidx 214 * @cpu: CPU whose TLB should be flushed 215 * @addr: virtual address of page to be flushed 216 * @idxmap: bitmap of mmu indexes to flush 217 * @bits: number of significant bits in address 218 * 219 * Similar to tlb_flush_page_mask, but with a bitmap of indexes. 220 */ 221 void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, 222 uint16_t idxmap, unsigned bits); 223 224 /* Similarly, with broadcast and syncing. */ 225 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr, 226 uint16_t idxmap, unsigned bits); 227 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced 228 (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits); 229 230 /** 231 * tlb_flush_range_by_mmuidx 232 * @cpu: CPU whose TLB should be flushed 233 * @addr: virtual address of the start of the range to be flushed 234 * @len: length of range to be flushed 235 * @idxmap: bitmap of mmu indexes to flush 236 * @bits: number of significant bits in address 237 * 238 * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), 239 * comparing only the low @bits worth of each virtual page. 240 */ 241 void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, 242 vaddr len, uint16_t idxmap, 243 unsigned bits); 244 245 /* Similarly, with broadcast and syncing. */ 246 void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr, 247 vaddr len, uint16_t idxmap, 248 unsigned bits); 249 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, 250 vaddr addr, 251 vaddr len, 252 uint16_t idxmap, 253 unsigned bits); 254 255 /** 256 * tlb_set_page_full: 257 * @cpu: CPU context 258 * @mmu_idx: mmu index of the tlb to modify 259 * @addr: virtual address of the entry to add 260 * @full: the details of the tlb entry 261 * 262 * Add an entry to @cpu tlb index @mmu_idx. All of the fields of 263 * @full must be filled, except for xlat_section, and constitute 264 * the complete description of the translated page. 265 * 266 * This is generally called by the target tlb_fill function after 267 * having performed a successful page table walk to find the physical 268 * address and attributes for the translation. 269 * 270 * At most one entry for a given virtual address is permitted. Only a 271 * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only 272 * used by tlb_flush_page. 273 */ 274 void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, 275 CPUTLBEntryFull *full); 276 277 /** 278 * tlb_set_page_with_attrs: 279 * @cpu: CPU to add this TLB entry for 280 * @addr: virtual address of page to add entry for 281 * @paddr: physical address of the page 282 * @attrs: memory transaction attributes 283 * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) 284 * @mmu_idx: MMU index to insert TLB entry for 285 * @size: size of the page in bytes 286 * 287 * Add an entry to this CPU's TLB (a mapping from virtual address 288 * @addr to physical address @paddr) with the specified memory 289 * transaction attributes. This is generally called by the target CPU 290 * specific code after it has been called through the tlb_fill() 291 * entry point and performed a successful page table walk to find 292 * the physical address and attributes for the virtual address 293 * which provoked the TLB miss. 294 * 295 * At most one entry for a given virtual address is permitted. Only a 296 * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only 297 * used by tlb_flush_page. 298 */ 299 void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, 300 hwaddr paddr, MemTxAttrs attrs, 301 int prot, int mmu_idx, vaddr size); 302 /* tlb_set_page: 303 * 304 * This function is equivalent to calling tlb_set_page_with_attrs() 305 * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided 306 * as a convenience for CPUs which don't use memory transaction attributes. 307 */ 308 void tlb_set_page(CPUState *cpu, vaddr addr, 309 hwaddr paddr, int prot, 310 int mmu_idx, vaddr size); 311 #else 312 static inline void tlb_init(CPUState *cpu) 313 { 314 } 315 static inline void tlb_destroy(CPUState *cpu) 316 { 317 } 318 static inline void tlb_flush_page(CPUState *cpu, vaddr addr) 319 { 320 } 321 static inline void tlb_flush_page_all_cpus(CPUState *src, vaddr addr) 322 { 323 } 324 static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr) 325 { 326 } 327 static inline void tlb_flush(CPUState *cpu) 328 { 329 } 330 static inline void tlb_flush_all_cpus(CPUState *src_cpu) 331 { 332 } 333 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) 334 { 335 } 336 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, 337 vaddr addr, uint16_t idxmap) 338 { 339 } 340 341 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) 342 { 343 } 344 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, 345 vaddr addr, 346 uint16_t idxmap) 347 { 348 } 349 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, 350 vaddr addr, 351 uint16_t idxmap) 352 { 353 } 354 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap) 355 { 356 } 357 358 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, 359 uint16_t idxmap) 360 { 361 } 362 static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, 363 vaddr addr, 364 uint16_t idxmap, 365 unsigned bits) 366 { 367 } 368 static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, 369 vaddr addr, 370 uint16_t idxmap, 371 unsigned bits) 372 { 373 } 374 static inline void 375 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, 376 uint16_t idxmap, unsigned bits) 377 { 378 } 379 static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, 380 vaddr len, uint16_t idxmap, 381 unsigned bits) 382 { 383 } 384 static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, 385 vaddr addr, 386 vaddr len, 387 uint16_t idxmap, 388 unsigned bits) 389 { 390 } 391 static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, 392 vaddr addr, 393 vaddr len, 394 uint16_t idxmap, 395 unsigned bits) 396 { 397 } 398 #endif 399 /** 400 * probe_access: 401 * @env: CPUArchState 402 * @addr: guest virtual address to look up 403 * @size: size of the access 404 * @access_type: read, write or execute permission 405 * @mmu_idx: MMU index to use for lookup 406 * @retaddr: return address for unwinding 407 * 408 * Look up the guest virtual address @addr. Raise an exception if the 409 * page does not satisfy @access_type. Raise an exception if the 410 * access (@addr, @size) hits a watchpoint. For writes, mark a clean 411 * page as dirty. 412 * 413 * Finally, return the host address for a page that is backed by RAM, 414 * or NULL if the page requires I/O. 415 */ 416 void *probe_access(CPUArchState *env, vaddr addr, int size, 417 MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); 418 419 static inline void *probe_write(CPUArchState *env, vaddr addr, int size, 420 int mmu_idx, uintptr_t retaddr) 421 { 422 return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); 423 } 424 425 static inline void *probe_read(CPUArchState *env, vaddr addr, int size, 426 int mmu_idx, uintptr_t retaddr) 427 { 428 return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); 429 } 430 431 /** 432 * probe_access_flags: 433 * @env: CPUArchState 434 * @addr: guest virtual address to look up 435 * @size: size of the access 436 * @access_type: read, write or execute permission 437 * @mmu_idx: MMU index to use for lookup 438 * @nonfault: suppress the fault 439 * @phost: return value for host address 440 * @retaddr: return address for unwinding 441 * 442 * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for 443 * the page, and storing the host address for RAM in @phost. 444 * 445 * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK. 446 * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags. 447 * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags. 448 * For simplicity, all "mmio-like" flags are folded to TLB_MMIO. 449 */ 450 int probe_access_flags(CPUArchState *env, vaddr addr, int size, 451 MMUAccessType access_type, int mmu_idx, 452 bool nonfault, void **phost, uintptr_t retaddr); 453 454 #ifndef CONFIG_USER_ONLY 455 /** 456 * probe_access_full: 457 * Like probe_access_flags, except also return into @pfull. 458 * 459 * The CPUTLBEntryFull structure returned via @pfull is transient 460 * and must be consumed or copied immediately, before any further 461 * access or changes to TLB @mmu_idx. 462 */ 463 int probe_access_full(CPUArchState *env, vaddr addr, int size, 464 MMUAccessType access_type, int mmu_idx, 465 bool nonfault, void **phost, 466 CPUTLBEntryFull **pfull, uintptr_t retaddr); 467 468 /** 469 * probe_access_mmu() - Like probe_access_full except cannot fault and 470 * doesn't trigger instrumentation. 471 * 472 * @env: CPUArchState 473 * @vaddr: virtual address to probe 474 * @size: size of the probe 475 * @access_type: read, write or execute permission 476 * @mmu_idx: softmmu index 477 * @phost: ptr to return value host address or NULL 478 * @pfull: ptr to return value CPUTLBEntryFull structure or NULL 479 * 480 * The CPUTLBEntryFull structure returned via @pfull is transient 481 * and must be consumed or copied immediately, before any further 482 * access or changes to TLB @mmu_idx. 483 * 484 * Returns: TLB flags as per probe_access_flags() 485 */ 486 int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size, 487 MMUAccessType access_type, int mmu_idx, 488 void **phost, CPUTLBEntryFull **pfull); 489 490 #endif 491 492 /* Hide the qatomic_read to make code a little easier on the eyes */ 493 static inline uint32_t tb_cflags(const TranslationBlock *tb) 494 { 495 return qatomic_read(&tb->cflags); 496 } 497 498 static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb) 499 { 500 #ifdef CONFIG_USER_ONLY 501 return tb->itree.start; 502 #else 503 return tb->page_addr[0]; 504 #endif 505 } 506 507 static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb) 508 { 509 #ifdef CONFIG_USER_ONLY 510 tb_page_addr_t next = tb->itree.last & TARGET_PAGE_MASK; 511 return next == (tb->itree.start & TARGET_PAGE_MASK) ? -1 : next; 512 #else 513 return tb->page_addr[1]; 514 #endif 515 } 516 517 static inline void tb_set_page_addr0(TranslationBlock *tb, 518 tb_page_addr_t addr) 519 { 520 #ifdef CONFIG_USER_ONLY 521 tb->itree.start = addr; 522 /* 523 * To begin, we record an interval of one byte. When the translation 524 * loop encounters a second page, the interval will be extended to 525 * include the first byte of the second page, which is sufficient to 526 * allow tb_page_addr1() above to work properly. The final corrected 527 * interval will be set by tb_page_add() from tb->size before the 528 * node is added to the interval tree. 529 */ 530 tb->itree.last = addr; 531 #else 532 tb->page_addr[0] = addr; 533 #endif 534 } 535 536 static inline void tb_set_page_addr1(TranslationBlock *tb, 537 tb_page_addr_t addr) 538 { 539 #ifdef CONFIG_USER_ONLY 540 /* Extend the interval to the first byte of the second page. See above. */ 541 tb->itree.last = addr; 542 #else 543 tb->page_addr[1] = addr; 544 #endif 545 } 546 547 /* current cflags for hashing/comparison */ 548 uint32_t curr_cflags(CPUState *cpu); 549 550 /* TranslationBlock invalidate API */ 551 #if defined(CONFIG_USER_ONLY) 552 void tb_invalidate_phys_addr(hwaddr addr); 553 #else 554 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs); 555 #endif 556 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); 557 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last); 558 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); 559 560 /* GETPC is the true target of the return instruction that we'll execute. */ 561 #if defined(CONFIG_TCG_INTERPRETER) 562 extern __thread uintptr_t tci_tb_ptr; 563 # define GETPC() tci_tb_ptr 564 #else 565 # define GETPC() \ 566 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) 567 #endif 568 569 /* The true return address will often point to a host insn that is part of 570 the next translated guest insn. Adjust the address backward to point to 571 the middle of the call insn. Subtracting one would do the job except for 572 several compressed mode architectures (arm, mips) which set the low bit 573 to indicate the compressed mode; subtracting two works around that. It 574 is also the case that there are no host isas that contain a call insn 575 smaller than 4 bytes, so we don't worry about special-casing this. */ 576 #define GETPC_ADJ 2 577 578 #if !defined(CONFIG_USER_ONLY) 579 580 /** 581 * iotlb_to_section: 582 * @cpu: CPU performing the access 583 * @index: TCG CPU IOTLB entry 584 * 585 * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that 586 * it refers to. @index will have been initially created and returned 587 * by memory_region_section_get_iotlb(). 588 */ 589 struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, 590 hwaddr index, MemTxAttrs attrs); 591 #endif 592 593 /** 594 * get_page_addr_code_hostp() 595 * @env: CPUArchState 596 * @addr: guest virtual address of guest code 597 * 598 * See get_page_addr_code() (full-system version) for documentation on the 599 * return value. 600 * 601 * Sets *@hostp (when @hostp is non-NULL) as follows. 602 * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp 603 * to the host address where @addr's content is kept. 604 * 605 * Note: this function can trigger an exception. 606 */ 607 tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, 608 void **hostp); 609 610 /** 611 * get_page_addr_code() 612 * @env: CPUArchState 613 * @addr: guest virtual address of guest code 614 * 615 * If we cannot translate and execute from the entire RAM page, or if 616 * the region is not backed by RAM, returns -1. Otherwise, returns the 617 * ram_addr_t corresponding to the guest code at @addr. 618 * 619 * Note: this function can trigger an exception. 620 */ 621 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, 622 vaddr addr) 623 { 624 return get_page_addr_code_hostp(env, addr, NULL); 625 } 626 627 #if defined(CONFIG_USER_ONLY) 628 void TSA_NO_TSA mmap_lock(void); 629 void TSA_NO_TSA mmap_unlock(void); 630 bool have_mmap_lock(void); 631 632 static inline void mmap_unlock_guard(void *unused) 633 { 634 mmap_unlock(); 635 } 636 637 #define WITH_MMAP_LOCK_GUARD() \ 638 for (int _mmap_lock_iter __attribute__((cleanup(mmap_unlock_guard))) \ 639 = (mmap_lock(), 0); _mmap_lock_iter == 0; _mmap_lock_iter = 1) 640 641 /** 642 * adjust_signal_pc: 643 * @pc: raw pc from the host signal ucontext_t. 644 * @is_write: host memory operation was write, or read-modify-write. 645 * 646 * Alter @pc as required for unwinding. Return the type of the 647 * guest memory access -- host reads may be for guest execution. 648 */ 649 MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); 650 651 /** 652 * handle_sigsegv_accerr_write: 653 * @cpu: the cpu context 654 * @old_set: the sigset_t from the signal ucontext_t 655 * @host_pc: the host pc, adjusted for the signal 656 * @host_addr: the host address of the fault 657 * 658 * Return true if the write fault has been handled, and should be re-tried. 659 */ 660 bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, 661 uintptr_t host_pc, abi_ptr guest_addr); 662 663 /** 664 * cpu_loop_exit_sigsegv: 665 * @cpu: the cpu context 666 * @addr: the guest address of the fault 667 * @access_type: access was read/write/execute 668 * @maperr: true for invalid page, false for permission fault 669 * @ra: host pc for unwinding 670 * 671 * Use the TCGCPUOps hook to record cpu state, do guest operating system 672 * specific things to raise SIGSEGV, and jump to the main cpu loop. 673 */ 674 G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, 675 MMUAccessType access_type, 676 bool maperr, uintptr_t ra); 677 678 /** 679 * cpu_loop_exit_sigbus: 680 * @cpu: the cpu context 681 * @addr: the guest address of the alignment fault 682 * @access_type: access was read/write/execute 683 * @ra: host pc for unwinding 684 * 685 * Use the TCGCPUOps hook to record cpu state, do guest operating system 686 * specific things to raise SIGBUS, and jump to the main cpu loop. 687 */ 688 G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, 689 MMUAccessType access_type, 690 uintptr_t ra); 691 692 #else 693 static inline void mmap_lock(void) {} 694 static inline void mmap_unlock(void) {} 695 #define WITH_MMAP_LOCK_GUARD() 696 697 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); 698 void tlb_set_dirty(CPUState *cpu, vaddr addr); 699 700 MemoryRegionSection * 701 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, 702 hwaddr *xlat, hwaddr *plen, 703 MemTxAttrs attrs, int *prot); 704 hwaddr memory_region_section_get_iotlb(CPUState *cpu, 705 MemoryRegionSection *section); 706 #endif 707 708 #endif 709