1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_DEFS_H 20 #define CPU_DEFS_H 21 22 #ifndef NEED_CPU_H 23 #error cpu.h included from common code 24 #endif 25 26 #include "config.h" 27 #include <inttypes.h> 28 #include "qemu/osdep.h" 29 #include "qemu/queue.h" 30 #ifndef CONFIG_USER_ONLY 31 #include "exec/hwaddr.h" 32 #endif 33 #include "exec/memattrs.h" 34 35 #ifndef TARGET_LONG_BITS 36 #error TARGET_LONG_BITS must be defined before including this header 37 #endif 38 39 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) 40 41 /* target_ulong is the type of a virtual address */ 42 #if TARGET_LONG_SIZE == 4 43 typedef int32_t target_long; 44 typedef uint32_t target_ulong; 45 #define TARGET_FMT_lx "%08x" 46 #define TARGET_FMT_ld "%d" 47 #define TARGET_FMT_lu "%u" 48 #elif TARGET_LONG_SIZE == 8 49 typedef int64_t target_long; 50 typedef uint64_t target_ulong; 51 #define TARGET_FMT_lx "%016" PRIx64 52 #define TARGET_FMT_ld "%" PRId64 53 #define TARGET_FMT_lu "%" PRIu64 54 #else 55 #error TARGET_LONG_SIZE undefined 56 #endif 57 58 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 59 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 60 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 61 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 62 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 63 64 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for 65 addresses on the same page. The top bits are the same. This allows 66 TLB invalidation to quickly clear a subset of the hash table. */ 67 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) 68 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) 69 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) 70 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) 71 72 #if !defined(CONFIG_USER_ONLY) 73 #define CPU_TLB_BITS 8 74 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) 75 /* use a fully associative victim tlb of 8 entries */ 76 #define CPU_VTLB_SIZE 8 77 78 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 79 #define CPU_TLB_ENTRY_BITS 4 80 #else 81 #define CPU_TLB_ENTRY_BITS 5 82 #endif 83 84 typedef struct CPUTLBEntry { 85 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 86 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 87 go directly to ram. 88 bit 3 : indicates that the entry is invalid 89 bit 2..0 : zero 90 */ 91 target_ulong addr_read; 92 target_ulong addr_write; 93 target_ulong addr_code; 94 /* Addend to virtual address to get host address. IO accesses 95 use the corresponding iotlb value. */ 96 uintptr_t addend; 97 /* padding to get a power of two size */ 98 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - 99 (sizeof(target_ulong) * 3 + 100 ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) + 101 sizeof(uintptr_t))]; 102 } CPUTLBEntry; 103 104 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 105 106 /* The IOTLB is not accessed directly inline by generated TCG code, 107 * so the CPUIOTLBEntry layout is not as critical as that of the 108 * CPUTLBEntry. (This is also why we don't want to combine the two 109 * structs into one.) 110 */ 111 typedef struct CPUIOTLBEntry { 112 hwaddr addr; 113 MemTxAttrs attrs; 114 } CPUIOTLBEntry; 115 116 #define CPU_COMMON_TLB \ 117 /* The meaning of the MMU modes is defined in the target code. */ \ 118 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ 119 CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ 120 CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ 121 CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ 122 target_ulong tlb_flush_addr; \ 123 target_ulong tlb_flush_mask; \ 124 target_ulong vtlb_index; \ 125 126 #else 127 128 #define CPU_COMMON_TLB 129 130 #endif 131 132 133 #define CPU_TEMP_BUF_NLONGS 128 134 #define CPU_COMMON \ 135 /* soft mmu support */ \ 136 CPU_COMMON_TLB \ 137 138 #endif 139