1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_DEFS_H 20 #define CPU_DEFS_H 21 22 #ifndef NEED_CPU_H 23 #error cpu.h included from common code 24 #endif 25 26 #include "config.h" 27 #include <inttypes.h> 28 #include "qemu/osdep.h" 29 #include "qemu/queue.h" 30 #include "tcg-target.h" 31 #ifndef CONFIG_USER_ONLY 32 #include "exec/hwaddr.h" 33 #endif 34 #include "exec/memattrs.h" 35 36 #ifndef TARGET_LONG_BITS 37 #error TARGET_LONG_BITS must be defined before including this header 38 #endif 39 40 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) 41 42 /* target_ulong is the type of a virtual address */ 43 #if TARGET_LONG_SIZE == 4 44 typedef int32_t target_long; 45 typedef uint32_t target_ulong; 46 #define TARGET_FMT_lx "%08x" 47 #define TARGET_FMT_ld "%d" 48 #define TARGET_FMT_lu "%u" 49 #elif TARGET_LONG_SIZE == 8 50 typedef int64_t target_long; 51 typedef uint64_t target_ulong; 52 #define TARGET_FMT_lx "%016" PRIx64 53 #define TARGET_FMT_ld "%" PRId64 54 #define TARGET_FMT_lu "%" PRIu64 55 #else 56 #error TARGET_LONG_SIZE undefined 57 #endif 58 59 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 60 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 61 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 62 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 63 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 64 65 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for 66 addresses on the same page. The top bits are the same. This allows 67 TLB invalidation to quickly clear a subset of the hash table. */ 68 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) 69 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) 70 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) 71 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) 72 73 #if !defined(CONFIG_USER_ONLY) 74 /* use a fully associative victim tlb of 8 entries */ 75 #define CPU_VTLB_SIZE 8 76 77 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 78 #define CPU_TLB_ENTRY_BITS 4 79 #else 80 #define CPU_TLB_ENTRY_BITS 5 81 #endif 82 83 /* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that 84 * the TLB is not unnecessarily small, but still small enough for the 85 * TLB lookup instruction sequence used by the TCG target. 86 * 87 * TCG will have to generate an operand as large as the distance between 88 * env and the tlb_table[NB_MMU_MODES - 1][0].addend. For simplicity, 89 * the TCG targets just round everything up to the next power of two, and 90 * count bits. This works because: 1) the size of each TLB is a largish 91 * power of two, 2) and because the limit of the displacement is really close 92 * to a power of two, 3) the offset of tlb_table[0][0] inside env is smaller 93 * than the size of a TLB. 94 * 95 * For example, the maximum displacement 0xFFF0 on PPC and MIPS, but TCG 96 * just says "the displacement is 16 bits". TCG_TARGET_TLB_DISPLACEMENT_BITS 97 * then ensures that tlb_table at least 0x8000 bytes large ("not unnecessarily 98 * small": 2^15). The operand then will come up smaller than 0xFFF0 without 99 * any particular care, because the TLB for a single MMU mode is larger than 100 * 0x10000-0xFFF0=16 bytes. In the end, the maximum value of the operand 101 * could be something like 0xC000 (the offset of the last TLB table) plus 102 * 0x18 (the offset of the addend field in each TLB entry) plus the offset 103 * of tlb_table inside env (which is non-trivial but not huge). 104 */ 105 #define CPU_TLB_BITS \ 106 MIN(8, \ 107 TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ 108 (NB_MMU_MODES <= 1 ? 0 : \ 109 NB_MMU_MODES <= 2 ? 1 : \ 110 NB_MMU_MODES <= 4 ? 2 : \ 111 NB_MMU_MODES <= 8 ? 3 : 4)) 112 113 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) 114 115 typedef struct CPUTLBEntry { 116 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 117 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 118 go directly to ram. 119 bit 3 : indicates that the entry is invalid 120 bit 2..0 : zero 121 */ 122 target_ulong addr_read; 123 target_ulong addr_write; 124 target_ulong addr_code; 125 /* Addend to virtual address to get host address. IO accesses 126 use the corresponding iotlb value. */ 127 uintptr_t addend; 128 /* padding to get a power of two size */ 129 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - 130 (sizeof(target_ulong) * 3 + 131 ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) + 132 sizeof(uintptr_t))]; 133 } CPUTLBEntry; 134 135 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 136 137 /* The IOTLB is not accessed directly inline by generated TCG code, 138 * so the CPUIOTLBEntry layout is not as critical as that of the 139 * CPUTLBEntry. (This is also why we don't want to combine the two 140 * structs into one.) 141 */ 142 typedef struct CPUIOTLBEntry { 143 hwaddr addr; 144 MemTxAttrs attrs; 145 } CPUIOTLBEntry; 146 147 #define CPU_COMMON_TLB \ 148 /* The meaning of the MMU modes is defined in the target code. */ \ 149 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ 150 CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ 151 CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ 152 CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ 153 target_ulong tlb_flush_addr; \ 154 target_ulong tlb_flush_mask; \ 155 target_ulong vtlb_index; \ 156 157 #else 158 159 #define CPU_COMMON_TLB 160 161 #endif 162 163 164 #define CPU_TEMP_BUF_NLONGS 128 165 #define CPU_COMMON \ 166 /* soft mmu support */ \ 167 CPU_COMMON_TLB \ 168 169 #endif 170