1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_DEFS_H 20 #define CPU_DEFS_H 21 22 #ifndef NEED_CPU_H 23 #error cpu.h included from common code 24 #endif 25 26 #include "qemu/host-utils.h" 27 #include "qemu/thread.h" 28 #ifndef CONFIG_USER_ONLY 29 #include "exec/hwaddr.h" 30 #endif 31 #include "exec/memattrs.h" 32 #include "hw/core/cpu.h" 33 34 #include "cpu-param.h" 35 36 #ifndef TARGET_LONG_BITS 37 # error TARGET_LONG_BITS must be defined in cpu-param.h 38 #endif 39 #ifndef NB_MMU_MODES 40 # error NB_MMU_MODES must be defined in cpu-param.h 41 #endif 42 #ifndef TARGET_PHYS_ADDR_SPACE_BITS 43 # error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h 44 #endif 45 #ifndef TARGET_VIRT_ADDR_SPACE_BITS 46 # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h 47 #endif 48 #ifndef TARGET_PAGE_BITS 49 # ifdef TARGET_PAGE_BITS_VARY 50 # ifndef TARGET_PAGE_BITS_MIN 51 # error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h 52 # endif 53 # else 54 # error TARGET_PAGE_BITS must be defined in cpu-param.h 55 # endif 56 #endif 57 58 #include "exec/target_long.h" 59 60 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 61 62 /* use a fully associative victim tlb of 8 entries */ 63 #define CPU_VTLB_SIZE 8 64 65 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 66 #define CPU_TLB_ENTRY_BITS 4 67 #else 68 #define CPU_TLB_ENTRY_BITS 5 69 #endif 70 71 #define CPU_TLB_DYN_MIN_BITS 6 72 #define CPU_TLB_DYN_DEFAULT_BITS 8 73 74 # if HOST_LONG_BITS == 32 75 /* Make sure we do not require a double-word shift for the TLB load */ 76 # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) 77 # else /* HOST_LONG_BITS == 64 */ 78 /* 79 * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == 80 * 2**34 == 16G of address space. This is roughly what one would expect a 81 * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel 82 * Skylake's Level-2 STLB has 16 1G entries. 83 * Also, make sure we do not size the TLB past the guest's address space. 84 */ 85 # ifdef TARGET_PAGE_BITS_VARY 86 # define CPU_TLB_DYN_MAX_BITS \ 87 MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 88 # else 89 # define CPU_TLB_DYN_MAX_BITS \ 90 MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 91 # endif 92 # endif 93 94 /* Minimalized TLB entry for use by TCG fast path. */ 95 typedef struct CPUTLBEntry { 96 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 97 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 98 go directly to ram. 99 bit 3 : indicates that the entry is invalid 100 bit 2..0 : zero 101 */ 102 union { 103 struct { 104 target_ulong addr_read; 105 target_ulong addr_write; 106 target_ulong addr_code; 107 /* Addend to virtual address to get host address. IO accesses 108 use the corresponding iotlb value. */ 109 uintptr_t addend; 110 }; 111 /* padding to get a power of two size */ 112 uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; 113 }; 114 } CPUTLBEntry; 115 116 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 117 118 119 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 120 121 #if !defined(CONFIG_USER_ONLY) 122 /* 123 * The full TLB entry, which is not accessed by generated TCG code, 124 * so the layout is not as critical as that of CPUTLBEntry. This is 125 * also why we don't want to combine the two structs. 126 */ 127 typedef struct CPUTLBEntryFull { 128 /* 129 * @xlat_section contains: 130 * - in the lower TARGET_PAGE_BITS, a physical section number 131 * - with the lower TARGET_PAGE_BITS masked off, an offset which 132 * must be added to the virtual address to obtain: 133 * + the ram_addr_t of the target RAM (if the physical section 134 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) 135 * + the offset within the target MemoryRegion (otherwise) 136 */ 137 hwaddr xlat_section; 138 139 /* 140 * @phys_addr contains the physical address in the address space 141 * given by cpu_asidx_from_attrs(cpu, @attrs). 142 */ 143 hwaddr phys_addr; 144 145 /* @attrs contains the memory transaction attributes for the page. */ 146 MemTxAttrs attrs; 147 148 /* @prot contains the complete protections for the page. */ 149 uint8_t prot; 150 151 /* @lg_page_size contains the log2 of the page size. */ 152 uint8_t lg_page_size; 153 154 /* 155 * Allow target-specific additions to this structure. 156 * This may be used to cache items from the guest cpu 157 * page tables for later use by the implementation. 158 */ 159 #ifdef TARGET_PAGE_ENTRY_EXTRA 160 TARGET_PAGE_ENTRY_EXTRA 161 #endif 162 } CPUTLBEntryFull; 163 #endif /* !CONFIG_USER_ONLY */ 164 165 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 166 /* 167 * Data elements that are per MMU mode, minus the bits accessed by 168 * the TCG fast path. 169 */ 170 typedef struct CPUTLBDesc { 171 /* 172 * Describe a region covering all of the large pages allocated 173 * into the tlb. When any page within this region is flushed, 174 * we must flush the entire tlb. The region is matched if 175 * (addr & large_page_mask) == large_page_addr. 176 */ 177 target_ulong large_page_addr; 178 target_ulong large_page_mask; 179 /* host time (in ns) at the beginning of the time window */ 180 int64_t window_begin_ns; 181 /* maximum number of entries observed in the window */ 182 size_t window_max_entries; 183 size_t n_used_entries; 184 /* The next index to use in the tlb victim table. */ 185 size_t vindex; 186 /* The tlb victim table, in two parts. */ 187 CPUTLBEntry vtable[CPU_VTLB_SIZE]; 188 CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; 189 CPUTLBEntryFull *fulltlb; 190 } CPUTLBDesc; 191 192 /* 193 * Data elements that are per MMU mode, accessed by the fast path. 194 * The structure is aligned to aid loading the pair with one insn. 195 */ 196 typedef struct CPUTLBDescFast { 197 /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ 198 uintptr_t mask; 199 /* The array of tlb entries itself. */ 200 CPUTLBEntry *table; 201 } CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); 202 203 /* 204 * Data elements that are shared between all MMU modes. 205 */ 206 typedef struct CPUTLBCommon { 207 /* Serialize updates to f.table and d.vtable, and others as noted. */ 208 QemuSpin lock; 209 /* 210 * Within dirty, for each bit N, modifications have been made to 211 * mmu_idx N since the last time that mmu_idx was flushed. 212 * Protected by tlb_c.lock. 213 */ 214 uint16_t dirty; 215 /* 216 * Statistics. These are not lock protected, but are read and 217 * written atomically. This allows the monitor to print a snapshot 218 * of the stats without interfering with the cpu. 219 */ 220 size_t full_flush_count; 221 size_t part_flush_count; 222 size_t elide_flush_count; 223 } CPUTLBCommon; 224 225 /* 226 * The entire softmmu tlb, for all MMU modes. 227 * The meaning of each of the MMU modes is defined in the target code. 228 * Since this is placed within CPUNegativeOffsetState, the smallest 229 * negative offsets are at the end of the struct. 230 */ 231 232 typedef struct CPUTLB { 233 CPUTLBCommon c; 234 CPUTLBDesc d[NB_MMU_MODES]; 235 CPUTLBDescFast f[NB_MMU_MODES]; 236 } CPUTLB; 237 238 /* This will be used by TCG backends to compute offsets. */ 239 #define TLB_MASK_TABLE_OFS(IDX) \ 240 ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) 241 242 #else 243 244 typedef struct CPUTLB { } CPUTLB; 245 246 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 247 248 /* 249 * This structure must be placed in ArchCPU immediately 250 * before CPUArchState, as a field named "neg". 251 */ 252 typedef struct CPUNegativeOffsetState { 253 CPUTLB tlb; 254 IcountDecr icount_decr; 255 } CPUNegativeOffsetState; 256 257 #endif 258