1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_DEFS_H 20 #define CPU_DEFS_H 21 22 #ifndef NEED_CPU_H 23 #error cpu.h included from common code 24 #endif 25 26 #include "qemu/host-utils.h" 27 #include "qemu/thread.h" 28 #include "qemu/queue.h" 29 #ifdef CONFIG_TCG 30 #include "tcg-target.h" 31 #endif 32 #ifndef CONFIG_USER_ONLY 33 #include "exec/hwaddr.h" 34 #endif 35 #include "exec/memattrs.h" 36 37 #include "cpu-param.h" 38 39 #ifndef TARGET_LONG_BITS 40 # error TARGET_LONG_BITS must be defined in cpu-param.h 41 #endif 42 #ifndef NB_MMU_MODES 43 # error NB_MMU_MODES must be defined in cpu-param.h 44 #endif 45 #ifndef TARGET_PHYS_ADDR_SPACE_BITS 46 # error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h 47 #endif 48 #ifndef TARGET_VIRT_ADDR_SPACE_BITS 49 # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h 50 #endif 51 #ifndef TARGET_PAGE_BITS 52 # ifdef TARGET_PAGE_BITS_VARY 53 # ifndef TARGET_PAGE_BITS_MIN 54 # error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h 55 # endif 56 # else 57 # error TARGET_PAGE_BITS must be defined in cpu-param.h 58 # endif 59 #endif 60 61 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) 62 63 /* target_ulong is the type of a virtual address */ 64 #if TARGET_LONG_SIZE == 4 65 typedef int32_t target_long; 66 typedef uint32_t target_ulong; 67 #define TARGET_FMT_lx "%08x" 68 #define TARGET_FMT_ld "%d" 69 #define TARGET_FMT_lu "%u" 70 #elif TARGET_LONG_SIZE == 8 71 typedef int64_t target_long; 72 typedef uint64_t target_ulong; 73 #define TARGET_FMT_lx "%016" PRIx64 74 #define TARGET_FMT_ld "%" PRId64 75 #define TARGET_FMT_lu "%" PRIu64 76 #else 77 #error TARGET_LONG_SIZE undefined 78 #endif 79 80 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 81 /* use a fully associative victim tlb of 8 entries */ 82 #define CPU_VTLB_SIZE 8 83 84 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 85 #define CPU_TLB_ENTRY_BITS 4 86 #else 87 #define CPU_TLB_ENTRY_BITS 5 88 #endif 89 90 #define CPU_TLB_DYN_MIN_BITS 6 91 #define CPU_TLB_DYN_DEFAULT_BITS 8 92 93 # if HOST_LONG_BITS == 32 94 /* Make sure we do not require a double-word shift for the TLB load */ 95 # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) 96 # else /* HOST_LONG_BITS == 64 */ 97 /* 98 * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == 99 * 2**34 == 16G of address space. This is roughly what one would expect a 100 * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel 101 * Skylake's Level-2 STLB has 16 1G entries. 102 * Also, make sure we do not size the TLB past the guest's address space. 103 */ 104 # define CPU_TLB_DYN_MAX_BITS \ 105 MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 106 # endif 107 108 typedef struct CPUTLBEntry { 109 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 110 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 111 go directly to ram. 112 bit 3 : indicates that the entry is invalid 113 bit 2..0 : zero 114 */ 115 union { 116 struct { 117 target_ulong addr_read; 118 target_ulong addr_write; 119 target_ulong addr_code; 120 /* Addend to virtual address to get host address. IO accesses 121 use the corresponding iotlb value. */ 122 uintptr_t addend; 123 }; 124 /* padding to get a power of two size */ 125 uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; 126 }; 127 } CPUTLBEntry; 128 129 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 130 131 /* The IOTLB is not accessed directly inline by generated TCG code, 132 * so the CPUIOTLBEntry layout is not as critical as that of the 133 * CPUTLBEntry. (This is also why we don't want to combine the two 134 * structs into one.) 135 */ 136 typedef struct CPUIOTLBEntry { 137 /* 138 * @addr contains: 139 * - in the lower TARGET_PAGE_BITS, a physical section number 140 * - with the lower TARGET_PAGE_BITS masked off, an offset which 141 * must be added to the virtual address to obtain: 142 * + the ram_addr_t of the target RAM (if the physical section 143 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) 144 * + the offset within the target MemoryRegion (otherwise) 145 */ 146 hwaddr addr; 147 MemTxAttrs attrs; 148 } CPUIOTLBEntry; 149 150 typedef struct CPUTLBDesc { 151 /* 152 * Describe a region covering all of the large pages allocated 153 * into the tlb. When any page within this region is flushed, 154 * we must flush the entire tlb. The region is matched if 155 * (addr & large_page_mask) == large_page_addr. 156 */ 157 target_ulong large_page_addr; 158 target_ulong large_page_mask; 159 /* host time (in ns) at the beginning of the time window */ 160 int64_t window_begin_ns; 161 /* maximum number of entries observed in the window */ 162 size_t window_max_entries; 163 /* The next index to use in the tlb victim table. */ 164 size_t vindex; 165 size_t n_used_entries; 166 } CPUTLBDesc; 167 168 /* 169 * Data elements that are shared between all MMU modes. 170 */ 171 typedef struct CPUTLBCommon { 172 /* Serialize updates to tlb_table and tlb_v_table, and others as noted. */ 173 QemuSpin lock; 174 /* 175 * Within dirty, for each bit N, modifications have been made to 176 * mmu_idx N since the last time that mmu_idx was flushed. 177 * Protected by tlb_c.lock. 178 */ 179 uint16_t dirty; 180 /* 181 * Statistics. These are not lock protected, but are read and 182 * written atomically. This allows the monitor to print a snapshot 183 * of the stats without interfering with the cpu. 184 */ 185 size_t full_flush_count; 186 size_t part_flush_count; 187 size_t elide_flush_count; 188 } CPUTLBCommon; 189 190 # define CPU_TLB \ 191 /* tlb_mask[i] contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ \ 192 uintptr_t tlb_mask[NB_MMU_MODES]; \ 193 CPUTLBEntry *tlb_table[NB_MMU_MODES]; 194 # define CPU_IOTLB \ 195 CPUIOTLBEntry *iotlb[NB_MMU_MODES]; 196 197 /* 198 * The meaning of each of the MMU modes is defined in the target code. 199 * Note that NB_MMU_MODES is not yet defined; we can only reference it 200 * within preprocessor defines that will be expanded later. 201 */ 202 #define CPU_COMMON_TLB \ 203 CPUTLBCommon tlb_c; \ 204 CPUTLBDesc tlb_d[NB_MMU_MODES]; \ 205 CPU_TLB \ 206 CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ 207 CPU_IOTLB \ 208 CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; 209 210 #else 211 212 #define CPU_COMMON_TLB 213 214 #endif 215 216 217 #define CPU_COMMON \ 218 /* soft mmu support */ \ 219 CPU_COMMON_TLB \ 220 221 #endif 222